74HC165: the parallel-in, serial-out shift register, live

The 74HC165 is an 8-bit parallel-load shift register: while SH/LD is low it copies eight inputs A to H into its stages, and once SH/LD is high each rising clock edge shifts the bits one place toward the serial output QH, with SER filling in behind. It is how a microcontroller reads eight buttons or switches through three pins.

TI's datasheet describes eight individual direct data inputs, A to H, "enabled by a low level at the shift/load (SH/LD) input", so the load does not wait for a clock: while SH/LD is low, each stage simply follows its input. This live circuit builds that with master-slave flip-flops that have their own asynchronous preset and clear: during a load, each stage is preset when its input is 1 and cleared when it is 0. (The six-NAND flip-flop of the 7474 page relies on gate delays to shift safely in a chain, so this zero-delay simulation uses the master-slave form for the stages.) When SH/LD goes high the stages form an ordinary shift register: SER into A, A into B, and so on, with H on QH and its complement on QH'. The clock is CLK OR CLK INH, which is why the datasheet says their functions are interchangeable: hold CLK INH high to ignore CLK, or hold CLK low and clock with CLK INH. QH shows H right after the load, so reading all eight bits takes one load and seven clocks. Chain chips by wiring QH of one to SER of the next. The live circuit opens loading (SH/LD = 0) with A to H at 0: set some inputs, then set SH/LD to 1 and clock CLK. Before the page is built, a 27-step sequence (load 10110010, shift on CLK, CLK INH raised while CLK is high and a blocked clock, shifts clocked by CLK INH, and a second load) is checked on QH and QH'.

Big circuit: pinch, scroll or tap + to zoom in, then drag to move around.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

8× D flip-flop with preset and clear: the stages A to H, each a master-slave pair of SR latches with preset and clear paths
16× AND: the parallel load: preset = load AND x and clear = load AND NOT x for each stage
9× NOT: load = NOT SH/LD, and NOT x for each parallel input
1× OR: the clock, CLK OR CLK INH

Step by step

Place inputs SH/LD, CLK, CLK INH, SER and A to H, and probes QH and QHbar.
Chain eight D flip-flops with preset and clear: SER into stage A's D, each Q into the next stage's D, with H's Q and Q' on QH and QHbar.
Clock all stages from CLK OR CLK INH.
For the parallel load, let load = NOT SH/LD drive each stage's preset through load AND x and its clear through load AND NOT x.
Load 10110010 (A to H), set SH/LD = 1, then pulse CLK: QH shows H, then G, F, and so on, one bit per rising edge.

74HC165 function table

SH/LD	CLK	CLK INH	What happens
0	X	X	Parallel load: the stages take A to H
1	1	X	No change
1	X	1	No change
1	0	rising	Shift toward QH, SER into the first stage
1	rising	0	Shift toward QH, SER into the first stage

74HC165 pinout

Pin	Name	Pin	Name
1	SH/LD	16	VCC
2	CLK	15	CLK INH
3	E	14	D
4	F	13	C
5	G	12	B
6	H	11	A
7	QH' (complement)	10	SER
8	GND	9	QH

X means the input does not matter. The function table and the 16-pin pinout are from TI's SN74HC165 datasheet (SCLS116H), checked 2026-10-25; it runs from 2 V to 6 V, and the datasheet adds that CLK INH should only be raised while CLK is high. The serial-in, parallel-out partner chip is the 74HC595; the 4-bit version of this circuit is the PISO shift register.

You can also read the full theory in the lesson on shift registers. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the 74HC165 shift register in the lab →

Frequently asked

How does the 74HC165 work?

Pull SH/LD low to copy the eight parallel inputs A to H into the register, then set it high and clock CLK: each rising edge shifts the bits one place toward QH, so the bits come out one at a time, H first, while SER shifts in behind them.

What is the difference between the 74HC165 and the 74HC595?

They are opposites. The 74HC165 is parallel-in, serial-out: it reads eight inputs into one data line. The 74HC595 is serial-in, parallel-out: it takes bits from one data line and drives eight outputs.

What is CLK INH on the 74HC165?

Clock inhibit. The internal clock is CLK OR CLK INH, so while CLK INH is high the register ignores CLK. Because the two are interchangeable, you can also hold CLK low and use a rising edge on CLK INH as the clock.

How do you read more than 8 inputs with 74HC165s?

Chain them: connect QH of the first chip to SER of the next and share SH/LD and CLK. Load all of them at once, then clock out 8 bits per chip.