74HC373 (74LS373): the octal transparent latch chip, live

The 74HC373 holds eight transparent D latches with tri-state outputs. While LE (latch enable) is HIGH, each output nQ follows its input nD; when LE goes LOW, the outputs hold the values the inputs had. The active-low output enable OE floats all eight outputs while it is HIGH. This live circuit has all eight latches.

TI's datasheet calls the eight latches transparent D-type latches and lists the jobs they suit: buffer registers, I/O ports, bidirectional bus drivers and working registers. The classic one is address latching on a multiplexed bus, where a processor puts an address on the same pins it later uses for data: a pulse on LE catches the address in a 74HC373, which keeps driving it while the pins move on to data. Each latch here is the gated D latch followed by a transistor-level tri-state buffer, so with OE high you can watch the outputs float while the latches keep their values. Compare its edge-triggered twin, the 74HC374, which has the same pins but loads only on a rising clock edge; D latch vs D flip-flop shows the difference on one bit. The live chip opens with LE high and OE low, so the outputs follow the inputs. Before the page is built, a 10-step sequence (transparent, latched while the inputs change, outputs floating and back, latching a new value) is checked on all eight outputs.

Big circuit: pinch, scroll or tap + to zoom in, then drag to move around.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

8× D latch: 1D to 8D, all enabled by LE
8× tri-state buffer: the outputs 1Q to 8Q, enabled by NOT OE (each 8 transistors)
1× NOT: the active-low OE

Step by step

Place inputs OE, LE, 1D to 8D and probes 1Q to 8Q.
Give each input a D latch enabled by LE.
Follow each latch with a tri-state buffer enabled by NOT OE.
With LE = 1, the outputs follow the inputs. Set LE = 0 and change the inputs: the outputs hold. Set OE = 1: they float.

74HC373 function table (each latch)

OE	LE	D	Q
0	1	1	1
0	1	0	0
0	0	X	held value
1	X	X	Z (high impedance)

74HC373 pinout

Pin	Name	Pin	Name
1	OE (active low)	20	VCC
2	1Q	19	8Q
3	1D	18	8D
4	2D	17	7D
5	2Q	16	7Q
6	3Q	15	6Q
7	3D	14	6D
8	4D	13	5D
9	4Q	12	5Q
10	GND	11	LE

X means the input does not matter; Z is high impedance. The behavior and the 20-pin pinout are from TI's SN74HC373 datasheet (SCLS140G), checked 2026-10-25; it runs from 2 V to 6 V. The 74HC374 uses the same pins, with CLK on pin 11 instead of LE.

You can also read the full theory in the lesson on the D latch. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the 74HC373 octal latch in the lab →

Frequently asked

What does the 74HC373 do?

It is an 8-bit transparent latch with tri-state outputs. While LE is high the outputs follow the D inputs; when LE goes low they keep the last values. OE high puts the outputs in high impedance without disturbing the stored data.

What is the difference between the 74HC373 and the 74HC374?

Same pinout, different storage: the 373 has transparent latches controlled by the level of LE, while the 374 has edge-triggered D flip-flops that load only on the rising edge of CLK.

What is the 74HC373 used for?

Holding a byte steady while its source moves on: latching the address from a multiplexed address/data bus, output ports, and registers on a shared bus, which is what its tri-state outputs are for.

What does transparent latch mean?

While enabled, the latch passes its input straight to its output, as if it were a wire, so every change on D appears on Q. It only stores when the enable goes inactive.