Half adder using 2-to-1 multiplexers (MUX), live

A half adder can be built from two 2-to-1 multiplexers and one NOT gate. Input A drives the select line of both muxes, so each mux picks between two half-rows of the truth table: the sum mux chooses B when A = 0 and NOT B when A = 1, and the carry mux chooses 0 when A = 0 and B when A = 1.

This is the multiplexer used as a function generator. Split the truth table on A: when A = 0 the half adder's sum is B and its carry is 0; when A = 1 the sum is NOT B and the carry is B. Each of those four entries is either a constant or B itself, so wire them to the mux data inputs and let A choose. The result is S = A XOR B and C = A AND B without a single XOR or AND gate. The same trick with 4-to-1 muxes and two select lines builds the full adder using 4-to-1 multiplexers, and any function of n + 1 variables fits in a 2ⁿ-to-1 mux this way, which is how FPGA lookup tables work. Compare the gate version, the half adder (one XOR and one AND). All four rows are checked before the page is built.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

2× 2-to-1 MUX: S: B or NOT B, and C: 0 or B, both selected by A
1× NOT: NOT B for the sum mux

Step by step

Place inputs A and B and probes S and C.
Split the truth table on A: for A = 0, S = B and C = 0; for A = 1, S = NOT B and C = B.
Sum mux: data 0 = B, data 1 = NOT B, select = A. Carry mux: data 0 = 0 (ground), data 1 = B, select = A.
Try all four rows: S is 1 when exactly one input is 1, and C only when both are.

Half adder truth table

A	B	Sum mux picks	S	Carry mux picks	C
0	0	B	0	0	0
0	1	B	1	0	0
1	0	NOT B	1	B	0
1	1	NOT B	0	B	1

Because A selects, each mux only has to produce a function of B, and every function of one variable is 0, 1, B or NOT B. That is the whole method in one line.

You can also read the full theory in the lesson on the multiplexer as a universal block. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the half adder using 2:1 multiplexers in the lab →

Frequently asked

How do you make a half adder using a multiplexer?

Use two 2-to-1 multiplexers with A on both select lines. For the sum, feed B into data input 0 and NOT B into data input 1; for the carry, feed 0 into input 0 and B into input 1.

How many multiplexers does a half adder need?

Two 2-to-1 multiplexers (one for the sum, one for the carry) plus one NOT gate for NOT B. With 4-to-1 muxes, A and B on the selects and constants on the data inputs, it needs no NOT gate at all.

Why can a multiplexer implement any logic function?

Because its select inputs pick one row of a truth table and its data inputs supply that row's value. Feed the data inputs with constants or the remaining variable and the mux reproduces the whole table.