CD4013: the CMOS dual D flip-flop chip, live

The CD4013 is a CMOS chip with two independent D flip-flops. Each copies its D input to Q on the rising edge of its CLOCK, and has SET and RESET inputs that are active HIGH and work at once, without the clock: SET = 1 forces Q to 1, RESET = 1 forces it to 0. This live circuit has both flip-flops.

TI's datasheet (CD4013B) puts it plainly: "The logic level present at the D input is transferred to the Q output during the positive-going transition of the clock pulse. Setting or resetting is independent of the clock and is accomplished by a high level on the set or reset line, respectively." That active-high SET and RESET is the main difference from the TTL-family 7474, whose preset and clear are active low, along with a different pinout and a supply range of 3 V to 18 V. The datasheet suggests two common uses: shift registers, and counters or toggles made by connecting the Q' output back to D, which divides a clock by two. Each flip-flop here is the six-NAND edge-triggered design with inverters on SET and RESET, which also reproduces the datasheet's last row: with SET and RESET both high, both Q and Q' are high. CLOCK is a plain switch here. The live chip opens with both RESET inputs high (both Q = 0): set RESET1 to 0, choose D1 and turn CLOCK1 on. Before the page is built, an 11-step sequence (reset, set, both edges with D at 1 and 0, the other flip-flop on its own clock, and SET = RESET = 1) is checked on all four outputs.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

2× D flip-flop with preset and clear: flip-flops 1 and 2, each six 3-input NANDs (an AND into a NAND each)
4× NOT: the active-high SET and RESET of each flip-flop into the gates' active-low preset and clear

Step by step

Place, for each flip-flop n, inputs Dn, CLOCKn, SETn, RESETn and probes Qn and Qnbar.
Build each as an edge-triggered D flip-flop with asynchronous preset and clear.
Drive the preset from NOT SET and the clear from NOT RESET, so both work when HIGH.
Keep SET and RESET low, put a value on D, and raise CLOCK: Q takes it. Raise SET or RESET to force Q at any time.

CD4013 function table (each flip-flop)

CLOCK	SET	RESET	D	Q	Q'
rising	0	0	0	0	1
rising	0	0	1	1	0
falling	0	0	X	no change	no change
X	0	1	X	0	1
X	1	0	X	1	0
X	1	1	X	1	1

CD4013 pinout

Pin	Name	Pin	Name
1	Q1	14	VDD
2	Q1'	13	Q2
3	CLOCK1	12	Q2'
4	RESET1	11	CLOCK2
5	D1	10	RESET2
6	SET1	9	D2
7	VSS	8	SET2

X means the input does not matter. The function table, the description and the 14-pin pinout are from TI's CD4013B datasheet (SCHS023E), checked 2026-10-25. Unused CMOS inputs, SET and RESET included, should be tied to VSS or VDD rather than left open.

You can also read the full theory in the lesson on the D flip-flop. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the CD4013 dual D flip-flop in the lab →

Frequently asked

What does the CD4013 do?

It contains two independent rising-edge D flip-flops, each with D, CLOCK, SET and RESET inputs and Q and Q' outputs. SET and RESET are active high and override the clock.

What is the difference between the CD4013 and the 7474?

Both are dual D flip-flops with asynchronous set and reset, but the CD4013's SET and RESET are active high while the 7474's preset and clear are active low, the pinouts differ, and the CD4013 is a 4000-series CMOS part that runs from 3 V to 18 V.

How do you make a toggle flip-flop with a CD4013?

Connect Q' back to D and keep SET and RESET low. Each rising clock edge then loads the opposite of Q, so the output toggles and divides the clock frequency by two.

What happens if SET and RESET are both high on a CD4013?

Both Q and Q' go high, as the datasheet's function table shows. It is not a useful storage state; the result when both are released depends on which one goes low last.