74HC125: the quad tri-state buffer chip, live

The 74HC125 holds four independent buffers with 3-state outputs, each with its own active-low output enable: while nOE is 0, nY copies nA; while nOE is 1, nY is high impedance (Z), as if it were disconnected. This live chip opens with buffers 1 and 2 enabled and 3 and 4 switched off.

TI's datasheet describes it as four independent buffers with 3-state outputs, where "each gate performs the Boolean function Y = A in positive logic". The point is the third state: a disabled output neither drives high nor low, so several outputs can share one wire, a bus, as long as only one is enabled at a time. The datasheet's application note puts it this way: "It is common to see all four channels of a device used together for controlling a 4-bit data bus, however each channel of the device can be used independently." It also suggests a pull-up or pull-down resistor where the line must stay at a known level while every output is off. Each buffer here is the tri-state buffer built from transistors, enabled by an inverter on its nOE. Compared with the 74HC244, which has eight buffers in two groups of four with one enable per group, the 74HC125 gives every buffer its own enable; the 74HC126 has the same pinout with active-high enables. Before the page is built, all 256 combinations of the four enables and four inputs are checked, Z included.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

4× tri-state buffer: 1Y to 4Y, each passing its nA when enabled (8 transistors each)
4× NOT: the active-low enables 1OE to 4OE

Step by step

Place inputs 1OE to 4OE and 1A to 4A, and probes 1Y to 4Y.
Feed each nA into a tri-state buffer whose output is nY.
Drive each buffer's enable from NOT nOE, so the buffer is on while nOE is 0.
Set 1OE = 0 and toggle 1A: 1Y follows. Set 1OE = 1: 1Y floats (Z) whatever 1A does.

74HC125 function table (each buffer)

nOE	nA	nY
0	1	1
0	0	0
1	X	Z (high impedance)

74HC125 pinout

Pin	Name	Pin	Name
1	1OE (active low)	14	VCC
2	1A	13	4OE (active low)
3	1Y	12	4A
4	2OE (active low)	11	4Y
5	2A	10	3OE (active low)
6	2Y	9	3A
7	GND	8	3Y

X means the input does not matter; Z means the output is not driven. The function table and the 14-pin pinout are from TI's SN74HC125 datasheet (SCLS104F), checked 2026-10-25; the active-high 74HC126 is from SCLS103F. The 74HC125 runs from 2 V to 6 V, and unused inputs must be tied to VCC or GND.

You can also read the full theory in the lesson on tri-state outputs. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the 74HC125 quad tri-state buffer in the lab →

Frequently asked

What does the 74HC125 do?

It contains four buffers with 3-state outputs. Each output copies its input while its own output enable (OE) is low, and goes to high impedance, effectively disconnected, while OE is high.

What is the difference between the 74HC125 and the 74HC126?

Only the enable polarity: the 74HC125's OE inputs are active low and the 74HC126's are active high. The pinout and the buffers are the same.

What is the difference between the 74HC125 and the 74HC244?

The 74HC125 is a 14-pin chip with four buffers, each with its own enable. The 74HC244 is a 20-pin chip with eight buffers in two groups of four, each group sharing one enable.

What does high impedance mean on the 74HC125?

The output is switched off: it neither sources nor sinks current, so whatever else is connected to the wire sets its level. That is what lets several outputs share a bus, one at a time.