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7493 (74LS93): the 4-bit binary ripple counter chip, live

The 7493 (74LS93) is a 4-bit binary ripple counter chip: a divide-by-2 stage (QA, clocked by CKA) and a divide-by-8 stage (QB, QC, QD, clocked by CKB). With QA wired to CKB it counts 0 to 15 in binary on the falling edges of CKA and wraps to 0. Both R0 inputs high clear it. This live circuit is wired that way.

Every stage is a toggle flip-flop clocked by the falling edge of the stage before it, so the count ripples through the chip: the classic ripple counter, packaged. TI's datasheet groups it with the 7490 and 7492 as four master-slave flip-flops with a divide-by-two counter and a three-stage counter, divide-by-eight in this case, and the same gated zero reset. Because the stages switch one after another, the outputs pass through brief in-between values on carries such as 0111 to 1000; a synchronous counter like the 74HC161 avoids that. The resets are also how a 7493 becomes a divide-by-N counter: wire the outputs that are 1 at N to R0(1) and R0(2), and the count clears as it reaches N. The live circuit opens held at zero (R0(1) = R0(2) = 1): set R0(1) to 0 and turn CKA on and off to count. Before the page is built, 42 steps (a clear, eighteen counts through 15 and back, a clear mid-count and one more count) are checked on all four outputs.

Big circuit: pinch, scroll or tap + to zoom in, then drag to move around.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

Step by step

  1. Place inputs CKA, R0(1), R0(2) and probes QA to QD.
  2. Make four toggle flip-flops (D = Q'). Clock QA from NOT CKA, QB from QA', QC from QB' and QD from QC': each Q' rises when its Q falls.
  3. Clear all four with R0(1) AND R0(2).
  4. Release the reset and pulse CKA: QD QC QB QA count 0000 to 1111 and wrap to 0000.

7493 count sequence (QA wired to CKB)

CountQDQCQBQA
00000
10001
20010
30011
40100
50101
60110
70111
81000
91001
101010
111011
121100
131101
141110
151111

7493 pinout

PinNamePinName
1CKB14CKA
2R0(1)13NC
3R0(2)12QA
4NC11QD
5VCC10GND
6NC9QB
7NC8QC

The count sequence and the 14-pin pinout are from TI's SN74LS93 datasheet (SDLS940A, shared with the 7490 and 7492), checked 2026-10-25. VCC is pin 5 and GND pin 10, unlike most 14-pin logic chips.

You can also read the full theory in the lesson on counters. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the 7493 4-bit binary counter in the lab →

Frequently asked

What does the 7493 do?

It is a 4-bit binary ripple counter: a divide-by-2 and a divide-by-8 stage in one chip. With QA connected to CKB and pulses into CKA, the outputs QD QC QB QA count from 0 to 15 and wrap around.

How do you make a divide-by-10 or divide-by-12 counter with a 7493?

Use the reset inputs: connect the outputs that are 1 at the count you want to reach to R0(1) and R0(2). For divide by 10, QD and QB (1010); for divide by 12, QD and QC (1100). The counter clears the moment it reaches that value.

What is the difference between the 7490, 7492 and 7493?

All three share a divide-by-2 stage and the same package style. The second stage divides by 5 in the 7490 (a decade counter), by 6 in the 7492 (divide by 12 overall) and by 8 in the 7493 (4-bit binary). Only the 7490 has set-to-nine inputs.

Is the 7493 synchronous or asynchronous?

Asynchronous (ripple): each flip-flop is clocked by the one before it, so a change ripples through the stages one after another. For a synchronous 4-bit counter use a 74161.