74HC374 (74LS374): the octal D flip-flop register chip, live

The 74HC374 is an 8-bit register: eight edge-triggered D flip-flops with tri-state outputs. On each rising edge of CLK, the outputs 1Q to 8Q take the values on 1D to 8D and then hold them, whatever the inputs do, until the next edge. The active-low output enable OE floats the outputs while it is HIGH. This live circuit has all eight flip-flops.

In TI's words, "on the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs", and OE only switches the outputs between driving and high impedance: "OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state." That makes it a ready-made 8-bit register for a bus: clock a value in, then enable its outputs only when it is this register's turn to drive the bus. Each flip-flop here is the master-slave D flip-flop followed by a transistor-level tri-state buffer. Its level-sensitive twin is the 74HC373. Here CLK is a plain switch. The live chip opens with OE low; the outputs are unknown until the first rising edge of CLK, as on a powered-up chip. Before the page is built, an 11-step sequence (load, inputs changing between edges, a load while the outputs float, and outputs back on) is checked on all eight outputs.

Big circuit: pinch, scroll or tap + to zoom in, then drag to move around.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

8× D flip-flop: 1D to 8D, all clocked by CLK (rising edge)
8× tri-state buffer: the outputs 1Q to 8Q, enabled by NOT OE (each 8 transistors)
1× NOT: the active-low OE

Step by step

Place inputs OE, CLK, 1D to 8D and probes 1Q to 8Q.
Give each input a D flip-flop clocked by CLK.
Follow each flip-flop with a tri-state buffer enabled by NOT OE.
Set a pattern on the D inputs and turn CLK on: the outputs load it. Change the inputs: nothing happens until the next rising edge.

74HC374 function table (each flip-flop)

OE	CLK	D	Q
0	rising	1	1
0	rising	0	0
0	not rising	X	held value
1	X	X	Z (the flip-flop still loads on a rising edge)

74HC374 pinout

Pin	Name	Pin	Name
1	OE (active low)	20	VCC
2	1Q	19	8Q
3	1D	18	8D
4	2D	17	7D
5	2Q	16	7Q
6	3Q	15	6Q
7	3D	14	6D
8	4D	13	5D
9	4Q	12	5Q
10	GND	11	CLK

X means the input does not matter; Z is high impedance. The behavior and the 20-pin pinout are from TI's SN74HC374 datasheet (SCLS141G), checked 2026-10-25; it runs from 2 V to 6 V. The 74HC373 has the same pinout with LE on pin 11.

You can also read the full theory in the lesson on registers. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the 74HC374 octal D flip-flop in the lab →

Frequently asked

What does the 74HC374 do?

It is an 8-bit register made of eight positive-edge-triggered D flip-flops with tri-state outputs. Each rising edge of CLK loads the eight D inputs; OE high puts the outputs in high impedance.

Does OE affect the stored data on the 74HC374?

No. TI's datasheet says OE does not affect the internal operation of the flip-flops: old data can be kept, or new data clocked in, while the outputs are in the high-impedance state.

What is the difference between the 74HC374 and the 74HC574?

The logic is the same; the 574 arranges the pins with all inputs on one side and all outputs on the other, which is easier to route on a circuit board.

What is the difference between the 74HC374 and the 74HC373?

The 374 loads on the rising edge of CLK, so its outputs change only once per clock; the 373 is transparent while LE is high, so its outputs follow the inputs for as long as LE stays high.