74HC244 (74LS244): the octal tri-state buffer chip, live
The 74HC244 is an octal buffer with tri-state outputs, organized as two groups of four. While a group's output enable (1OE or 2OE, active low) is LOW, each output nYk copies its input nAk; while it is HIGH, the group's four outputs float (high impedance), as if disconnected. That is how many chips can share one bus. This live circuit has both groups.
TI's datasheet says the 74HC244 is designed for 3-state memory address drivers, clock drivers and bus-oriented receivers and transmitters, and describes it as "two 4-bit buffers and drivers with separate output-enable (OE) inputs" that pass noninverted data when OE is low and go to high impedance when it is high. Each of the eight buffers here is the transistor-level tri-state buffer (eight transistors), so you can watch an output float: the simulator shows a floating output as Z. A floating output is the point of the chip: on a shared bus exactly one driver is enabled at a time and every other one lets go, so their outputs never fight. The two groups have separate enables, so one chip can buffer a 4-bit address one way and a 4-bit status the other, or both halves can be tied together into an 8-bit buffer. The live chip opens with both enables LOW and all inputs 0. Before the page is built, 64 steps (every 4-bit pattern on group 1, its complement on group 2, with each group enabled and disabled) are checked on all eight outputs, the floating ones included.
Open this circuit in the lab →
What you need
- 8× tri-state buffer: nAk to nYk, each 8 transistors: an inverter on A, an inverter on EN and a tri-state inverter
- 2× NOT: the active-low enables: EN = NOT 1OE and NOT 2OE
Step by step
- Place inputs
1OE,2OE,1A1to1A4,2A1to2A4, and probes1Y1to2Y4. - Put a tri-state buffer between each A input and its Y output.
- Enable group 1's four buffers from NOT 1OE and group 2's from NOT 2OE.
- With 1OE = 0, toggle 1A1: 1Y1 follows. Set 1OE = 1: all four group 1 outputs float (Z), while group 2 keeps working.
74HC244 function table (each buffer)
| OE | A | Y |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | X | Z (high impedance) |
74HC244 pinout
| Pin | Name | Pin | Name |
|---|---|---|---|
| 1 | 1OE (active low) | 20 | VCC |
| 2 | 1A1 | 19 | 2OE (active low) |
| 3 | 2Y4 | 18 | 1Y1 |
| 4 | 1A2 | 17 | 2A4 |
| 5 | 2Y3 | 16 | 1Y2 |
| 6 | 1A3 | 15 | 2A3 |
| 7 | 2Y2 | 14 | 1Y3 |
| 8 | 1A4 | 13 | 2A2 |
| 9 | 2Y1 | 12 | 1Y4 |
| 10 | GND | 11 | 2A1 |
X means the input does not matter; Z is the floating, high-impedance state. The behavior and the 20-pin pinout are from TI's SN74HC244 datasheet, checked 2026-10-25; it runs from 2 V to 6 V. The two groups' pins interleave: group 1's inputs are on the left side and outputs on the right, group 2 the other way round.
You can also read the full theory in the lesson on tri-state buffers. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.
Build more parts from gates
Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.
Open the 74HC244 octal buffer in the lab →Frequently asked
What does the 74HC244 do?
It is an octal (8-bit) buffer and line driver with tri-state outputs, in two groups of four. With a group's active-low output enable LOW, its outputs copy its inputs; with it HIGH, those outputs go to high impedance.
What is a tri-state output?
An output with a third state besides 0 and 1: high impedance, where it neither drives high nor low and behaves as if disconnected. It lets several outputs share one wire, as long as only one is enabled at a time.
What is the difference between the 74HC244 and the 74HC245?
The 244 is a one-way buffer: data goes from the A side to the Y side. The 245 is a bidirectional transceiver with a direction input, used where data must flow both ways on a bus.
Does the 74HC244 invert the data?
No. The datasheet describes it as passing noninverted data from the A inputs to the Y outputs while the output enable is low.