The race-around condition in a JK flip-flop, live

The race-around condition is what happens when a level-triggered JK latch has J = K = 1 while its clock is high: the output toggles, the new value feeds straight back to the gates, it toggles again, and it keeps toggling for as long as the clock stays high, so the final value is unpredictable. This live latch shows it: the simulator reports the output as oscillating.

A JK latch made of four NAND gates feeds its own outputs back to its input gates (J is gated with Q' and K with Q), which is what makes J = K = 1 a toggle instead of the SR latch's forbidden input. But with a level-triggered clock, the toggle is not a single event: as soon as Q changes, the input gates see the new Q and Q' and start the next toggle, and this repeats every few gate delays while CLK is 1. In real hardware the output oscillates and settles at whatever value it happens to have when the clock falls; in this zero-delay simulator the loop never settles, and the simulator marks the outputs as oscillating instead of 0 or 1. The cure is to make sure the toggle can happen only once per clock pulse: the master-slave JK flip-flop (two latches with opposite clocks), or an edge-triggered flip-flop, or a clock pulse shorter than the gate delay round the loop, which is hard to guarantee. This latch also has an active-low clear, CLR, on the Q' gate: without it, a latch that has just powered up could not be set at all in this simulator, because J is gated by Q' and K by Q, and both start unknown. Try it: the circuit opens with CLR = 0 (Q cleared to 0) and J = K = 1. Set CLR to 1, then set CLK to 1 and watch Q race. Before the page is built, a 12-step sequence is checked: clear, set, hold, reset, hold, the oscillation with J = K = 1 and CLK = 1, a clear that stops it, and a clean set afterwards.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

2× AND + 2 NAND: the input gates n1 = NAND(J, CLK, Q') and n2 = NAND(K, CLK, Q), each 3-input NAND an AND into a NAND
2× NAND + 1 AND: the cross-coupled latch: Q = NAND(n1, Q'), Q' = NAND(n2, Q, CLR)

Step by step

Place inputs J, K, CLK, CLR and probes Q and Qbar.
Cross-couple two NAND gates as an SR latch with active-low inputs n1 and n2, and give the Q' gate a third input, CLR, so that CLR = 0 clears the latch.
Gate the inputs with the clock and the outputs: n1 = NAND(J, CLK, Q'), n2 = NAND(K, CLK, Q).
Clear it (CLR = 0, then 1) and check the normal cases with CLK = 1: J = 1, K = 0 sets Q; J = 0, K = 1 resets it; CLK = 0 holds.
Now hold CLK at 1 with J = K = 1: Q never settles. That is the race-around condition.

The checked sequence

Step	CLR	J	K	CLK	Q	What happens
1	0	0	0	0	0	Clear
2	1	0	0	0	0	Clear released: hold
3	1	1	0	1	1	Set
4	1	1	0	0	1	Clock low: hold
5	1	0	1	0	1	Inputs change, still holding
6	1	0	1	1	0	Reset
7	1	0	1	0	0	Hold
8	1	1	1	0	0	J = K = 1, but the clock is low: hold
9	1	1	1	1	oscillates	Race-around: toggles for as long as CLK is 1
10	1	1	1	0	0 or 1	Clock low again: the latch keeps whichever value it had
11	0	1	1	0	0	Clear: a known state again
12	1	1	0	1	1	A normal set works

Step 10 cannot be predicted, which is the whole problem: the value left behind depends on exactly when the clock fell during the oscillation. A master-slave or edge-triggered JK flip-flop gives a single, predictable toggle per clock instead; see the JK flip-flop lesson and the JK flip-flop build.

You can also read the full theory in the lesson on the JK flip-flop. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the Race-around condition (JK latch) in the lab →

Frequently asked

What is the race-around condition?

In a level-triggered JK latch with J = K = 1, the output toggles while the clock is high, and because the outputs feed back to the input gates, it toggles again and again until the clock goes low. The final state is unpredictable.

Why does the race-around condition occur?

Because the clock pulse is longer than the time it takes a change of Q to travel back through the input gates. During one long clock pulse the latch can toggle many times instead of once.

How do you avoid the race-around condition?

Use a master-slave JK flip-flop, where the master latch is open while the clock is high and the slave only while it is low, so the output can change only once per clock; or use an edge-triggered flip-flop. Making the clock pulse shorter than the loop delay also works in theory but is hard to guarantee.

Does the race-around condition happen in an SR latch?

No. In an SR latch the input S = R = 1 is simply forbidden; there is no feedback from the outputs into the input gates, so there is nothing to race. The JK latch adds that feedback to turn J = K = 1 into a toggle, and the race comes with it.