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7492 (74LS92): the divide-by-12 counter chip, live

The 7492 (74LS92) is a divide-by-12 counter chip: a divide-by-2 stage (QA, clocked by CKA) and a divide-by-6 stage (QB, QC, QD, clocked by CKB). With QA wired to CKB, twelve falling edges on CKA bring it back to 0000, so QD runs at one twelfth of the clock. This live circuit is wired that way.

It comes from the same TI datasheet as the 7490 and the 7493: four master-slave flip-flops and a three-stage counter whose cycle is divide-by-six. Its count is not plain binary: QD QC QB QA run 0000 to 0101, then jump to 1000 to 1101, because the divide-by-6 section is a divide-by-3 (QB, QC: 00, 01, 10) followed by a divide-by-2 (QD, toggled each time QC falls). That makes the outputs useful for timekeeping, where twelve and six turn up often: QD alone is a clean divide-by-12 square wave, and its divide-by-6 section, after the divide-by-10 of a 7490, gives the divide-by-60 of a seconds or minutes counter. The clocks act on the falling edge, as the inverted clock inputs in the datasheet's logic diagram show, and the two R0 inputs, both high, clear the count. The live circuit opens held at zero (R0(1) = R0(2) = 1): set R0(1) to 0 and turn CKA on and off to count. Before the page is built, 34 steps (a clear, fourteen counts through the whole 12-state sequence, a clear mid-count and one more count) are checked on all four outputs.

Big circuit: pinch, scroll or tap + to zoom in, then drag to move around.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

Step by step

  1. Place inputs CKA, R0(1), R0(2) and probes QA to QD.
  2. Make QA a toggle flip-flop clocked by NOT CKA.
  3. Make QB and QC count 0, 1, 2 on QA's falling edge (clock them from QA'): DB = NOR(QB, QC), DC = QB.
  4. Make QD a toggle flip-flop clocked by QC', so it flips each time the divide-by-3 wraps.
  5. Clear all four with R0(1) AND R0(2), release, and pulse CKA: 0000, 0001, ..., 0101, 1000, ..., 1101, then 0000.

7492 count sequence (QA wired to CKB)

CountQDQCQBQA
00000
10001
20010
30011
40100
50101
61000
71001
81010
91011
101100
111101

7492 pinout

PinNamePinName
1CKB14CKA
2NC13NC
3NC12QA
4NC11QB
5VCC10GND
6R0(1)9QC
7R0(2)8QD

The count sequence and the 14-pin pinout are from TI's SN74LS92 datasheet (SDLS940A, shared with the 7490 and 7493), checked 2026-10-25. Note that the 7492's output pins differ from the 7490's and 7493's (QB is on pin 11 here), and that VCC is pin 5 and GND pin 10.

You can also read the full theory in the lesson on counters. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the 7492 divide-by-12 counter in the lab →

Frequently asked

What does the 7492 do?

It is a divide-by-12 counter: a divide-by-2 stage and a divide-by-6 stage in one 14-pin chip. Connect QA to CKB and count into CKA, and the four outputs step through 12 states, so QD toggles at one twelfth of the input frequency.

Why does the 7492 count skip from 5 to 8?

Its divide-by-6 stage is a divide-by-3 (QB and QC) followed by a divide-by-2 (QD). QB and QC only count 0, 1, 2, so the binary values 6 and 7 (0110, 0111) never occur; after 0101 the divide-by-3 wraps and QD sets, giving 1000.

What is the 7492 used for?

Dividing a frequency by 12, 6, 3 or 2, for example in clocks and timers, where a divide-by-6 and a divide-by-10 (7490) together count the 60 seconds of a minute.

Does the 7492 count on the rising or falling edge?

On the falling edge: its flip-flops have inverted clock inputs in the datasheet's logic diagram, like the 7490 and 7493.