74LS76: the dual JK flip-flop chip, live

The 74LS76 holds two JK flip-flops with active-low preset (PRE) and clear (CLR). The 74LS76A triggers on the falling edge of CLK: J = 1, K = 0 sets Q, J = 0, K = 1 resets it, J = K = 0 holds and J = K = 1 toggles. PRE and CLR override the clock. This live circuit has both flip-flops.

TI's datasheet (SN54LS76A/SN74LS76A) describes the 'LS76A as "two independent negative-edge-triggered flip-flops": J and K must be stable for a setup time before the clock's high-to-low transition, and the preset and clear are asynchronous active-low inputs that, when low, override the clock and data inputs. (The older 7476 in the same datasheet is a master-slave part instead.) Each flip-flop here is a master-slave D flip-flop with asynchronous set and clear, clocked through an inverter so it changes on the falling edge, with the JK logic in front: D = J Q' + K' Q, which is the standard way to turn a D flip-flop into a JK (see the flip-flop conversions). Because the master and slave never both pass data, J = K = 1 toggles exactly once per clock, with no race-around. With PRE and CLR both low the chip drives both outputs high, a state the datasheet calls nonstable; the outputs here reproduce it. Note the unusual power pins, VCC on 5 and GND on 13. CLK is a plain switch here. The live chip opens with both CLR inputs low (Q = 0) and J = K = 1: set 1CLR to 1 and turn 1CLK on and off to toggle 1Q. Before the page is built, a 25-step sequence (clear, hold, set, reset, toggles, the second flip-flop toggling on its own clock, preset and the both-low state) is checked on all four outputs.

Big circuit: pinch, scroll or tap + to zoom in, then drag to move around.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

2× D flip-flop with set and clear: the two flip-flops (master-slave), clocked through an inverter for the falling edge
4× AND + 2 OR + 2 NOT: the JK logic of each: D = J Q' + K' Q
6× NOT: NOT CLK, NOT PRE and NOT CLR for each flip-flop
2× NOR + 4 OR: both outputs high while PRE and CLR are both low, as on the chip

Step by step

Place, for each flip-flop n, inputs nJ, nK, nCLK, nPRE, nCLR and probes nQ and nQbar.
Feed a D flip-flop with D = J Q' + K' Q, clocked by NOT CLK so it changes on the falling edge.
Wire NOT PRE to its set and NOT CLR to its clear, so both act when LOW.
Clear it, set J = K = 1 and pulse CLK: Q toggles once per falling edge.

74LS76A function table (each flip-flop)

PRE	CLR	CLK	J	K	Q	Q'
0	1	X	X	X	1	0
1	0	X	X	X	0	1
0	0	X	X	X	1 (nonstable)	1 (nonstable)
1	1	falling	0	0	no change	no change
1	1	falling	1	0	1	0
1	1	falling	0	1	0	1
1	1	falling	1	1	toggle	toggle
1	1	1	X	X	no change	no change

74LS76 pinout

Pin	Name	Pin	Name
1	1CLK	16	1K
2	1PRE (active low)	15	1Q
3	1CLR (active low)	14	1Q'
4	1J	13	GND
5	VCC	12	2K
6	2CLK	11	2Q
7	2PRE (active low)	10	2Q'
8	2CLR (active low)	9	2J

X means the input does not matter. The function table (for the 'LS76A) and the 16-pin pinout are from TI's SN74LS76A datasheet (SDLS121), checked 2026-10-25; the 7476 in the same datasheet is a positive-pulse master-slave version with the same pins.

You can also read the full theory in the lesson on the JK flip-flop. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the 74LS76 dual JK flip-flop in the lab →

Frequently asked

What does the 74LS76 do?

It contains two independent JK flip-flops with asynchronous active-low preset and clear. The 74LS76A changes on the falling edge of its clock: it can hold, set, reset or toggle, depending on J and K.

Is the 74LS76 edge triggered?

The 74LS76A is negative-edge triggered: J and K are read at the clock's high-to-low transition. The older 7476 is a master-slave (pulse-triggered) flip-flop.

How do you make a T flip-flop with a 74LS76?

Tie J and K together as the T input (or both high for a free toggle). With T = 1 each falling clock edge toggles Q, which divides the clock by two.

Why are the 74LS76's power pins 5 and 13?

That is its pinout: VCC on pin 5 and GND on pin 13, not the corner pins most logic chips use, so check it before wiring.