CD4081 (CD4081B): the quad 2-input AND gate chip, live

The CD4081 is a 4000-series CMOS chip with four 2-input AND gates: J = A AND B, K = C AND D, L = E AND F and M = G AND H. It runs from 3 V to 18 V and shares its pinout with the CD4011 and CD4001, not the 7408. This live chip has all four gates.

TI's datasheet (from Harris Semiconductor) groups the CD4081B with the triple 3-input CD4073B and the dual 4-input CD4082B: AND gates that "provide the system designer with direct implementation of the AND function and supplement the existing family of CMOS gates", for supplies from 3 V to 18 V. CMOS has no single-stage AND: the natural gate is NAND, so an AND is a NAND followed by an inverter, the CMOS AND each gate here is built from. The pins follow the 4000-series quad layout of the CD4011 and CD4001; the TTL-family 7408 puts its outputs on pins 3, 6, 8 and 11 instead, so check which chip you have. An AND gate passes a signal only while an enable is high, which is the everyday use: gating a clock, or switching a signal on with a control line. All 256 combinations of the eight inputs are checked before the page is built.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

4× 2-input AND: J from A, B; K from C, D; L from E, F; M from G, H

Step by step

Power the chip: VDD on pin 14 and VSS on pin 7, anywhere from 3 V to 18 V.
Each gate has two inputs and one output; find their pins in the pinout below.
Tie every unused input to VCC or GND: a floating CMOS input can drift and draw current.
Set all two inputs of one gate to 1: its output goes to 1. Any 0 on an input gives 0.

CD4081 pinout

Pin	Name	Pin	Name
1	A	14	VDD
2	B	13	H
3	J	12	G
4	K	11	M
5	C	10	L
6	D	9	F
7	VSS	8	E

2-input AND truth table (each gate)

A	B	Y
0	0	0
0	1	0
1	0	0
1	1	1

Pin numbers and names are from TI's CD4081B (SCHS057C) datasheet, checked 2026-10-25. Each gate is independent; the chip only shares the power pins.

You can also read the full theory in the lesson on the AND gate. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

Build more parts from gates

half adder full adder half subtractor full subtractor 2:1 multiplexer 4:1 multiplexer XOR gate from NAND gates 2-to-4 decoder SR latch D flip-flop JK flip-flop T flip-flop 4-bit shift register 4-bit ripple carry adder D latch 1-to-4 demultiplexer 4-bit magnitude comparator 4-bit ring counter 4-bit Johnson counter 4-to-2 priority encoder 4-bit synchronous counter 3-to-8 decoder 8-to-1 multiplexer 4-bit carry lookahead adder half adder from NAND gates 2-bit comparator BCD to 7-segment decoder 4-bit up/down counter decade counter 2-bit multiplier 4-bit ALU 4-bit array multiplier NOT, AND, OR and NOR from NAND NOT, OR, AND and XOR from NOR full adder from NAND gates SR latch from NAND gates parity generator and checker 4-bit adder/subtractor BCD adder 4-bit universal shift register mod-6 counter 4-bit ripple counter binary to Gray code converter half adder from NOR gates full adder from NOR gates 4-bit register with parallel load 1011 sequence detector binary to BCD converter D flip-flop from NAND gates 1-bit ALU CMOS inverter CMOS NAND gate CMOS NOR gate PISO shift register SR flip-flop from NAND gates BCD to excess-3 code converter Hamming (7,4) code encoder and corrector traffic light controller 4-bit barrel shifter CMOS AND gate CMOS OR gate CMOS XOR gate 1-bit magnitude comparator half subtractor from NAND gates full subtractor from NAND gates 8-to-3 encoder Gray to binary converter 4-to-16 decoder full adder using 4:1 multiplexers edge detector serial adder 4-bit carry-select adder 4-bit Kogge-Stone adder 4-bit carry-skip adder 4x4 Wallace tree multiplier 8-bit adder frequency divider (by 2, 4 and 3)switch debouncer (SR latch)3-bit Gray code counter Mealy machine (1011 detector)master-slave JK flip-flop (NAND)half subtractor from NOR gates 1-to-8 demultiplexer excess-3 to BCD code converter vending machine FSM 4-bit carry-save adder 3-bit synchronous counter (JK)CMOS transmission gate tri-state buffer (CMOS)2-to-1 mux from transmission gates mod-5 counter flip-flop conversion (JK to D)8-bit ALU decimal to BCD encoder BCD to decimal decoder 4-to-1 mux from 2-to-1 muxes XOR gate from NOR gates 4-bit LFSR 74LS138 decoder BCD subtractor 74181 ALU CMOS AOI gate (AOI21)D latch vs D flip-flop 74LS47 BCD to 7-segment decoder 74HC595 shift register 7400 quad NAND gate chip 7402 quad NOR gate chip 7404 hex inverter chip 7408 quad AND gate chip 7432 quad OR gate chip 7486 quad XOR gate chip 7474 dual D flip-flop 74HC165 shift register CD4017 decade counter 74LS283 4-bit adder 74LS90 decade counter 74HC161 4-bit counter 74HC151 8-to-1 multiplexer 74HC157 quad 2-to-1 multiplexer 74HC139 dual 2-to-4 decoder CD4511 BCD to 7-segment decoder 7492 divide-by-12 counter 7493 4-bit binary counter 74HC244 octal buffer Race-around condition (JK latch)74HC373 octal latch 74HC374 octal D flip-flop Turnstile state machine 1-to-2 demultiplexer half adder using 2:1 multiplexers register file (4 x 4-bit)digital PWM generator CD4013 dual D flip-flop 74LS76 dual JK flip-flop 7410 triple 3-input NAND chip 7411 triple 3-input AND chip 7420 dual 4-input NAND chip CD4011 quad 2-input NAND chip CD4001 quad 2-input NOR chip CD4069 hex inverter chip 74HC164 8-bit shift register

Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the CD4081 quad 2-input AND chip in the lab →

Frequently asked

What is the CD4081?

A 4000-series CMOS chip with four 2-input AND gates, for supplies from 3 V to 18 V. Each output is HIGH only when both of its inputs are HIGH.

What is the CD4081 pinout?

Pin 1 A, 2 B, 3 J, 4 K, 5 C, 6 D, 7 VSS, 8 E, 9 F, 10 L, 11 M, 12 G, 13 H, 14 VDD, with J = A AND B, K = C AND D, L = E AND F and M = G AND H.

Is the CD4081 the same as the 7408?

Same logic, different pinout and supply range. The CD4081's outputs are on pins 3, 4, 10 and 11, the 7408's (and 74HC08's) on 3, 6, 8 and 11, so one cannot replace the other in a socket. The CD4081 runs from 3 V to 18 V.

How is a CMOS AND gate built?

As a NAND gate followed by an inverter. In CMOS the inverting gates (NOT, NAND, NOR) are the single-stage ones, so a non-inverting AND needs the extra stage.