74LS193 (74HC193): the 4-bit up/down counter chip, live

The 74LS193 is a synchronous 4-bit binary counter with two clocks: it counts up on a rising edge of UP and down on a rising edge of DOWN, the other clock held high. LOAD (active low) presets the count from inputs A to D, CLR (active high) clears it, and CO and BO pulse low on overflow and underflow for cascading. This live circuit is the whole chip.

TI's datasheet describes the '193 as a synchronous reversible (up/down) counter "having a complexity of 55 equivalent gates", where "synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other", which "eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters". The direction is set by which count input is pulsed while the other is high. LOAD presets the outputs to the data inputs independently of the count pulses, which lets the chip divide by any number up to 16 (a modulo-N divider), CLR forces all outputs low regardless of the count and LOAD inputs, and for longer counts the borrow and carry outputs feed the DOWN and UP inputs of the next chip. This version models that behavior with its own logic rather than copying the chip's gate diagram: four master-slave D flip-flops with asynchronous preset and clear share one clock, UP AND DOWN, which rises when the pulsed input returns high; a two-NAND latch remembers which input went low; and the next count is Q + 1 or Q - 1, where a bit toggles when every lower bit is 1 (counting up) or 0 (counting down), as in the up/down counter. LOAD drives each flip-flop's preset or clear from its data bit, and CLR overrides LOAD. The live chip opens with CLR high and UP low (so the direction latch starts in a known state): set CLR to 0, then turn UP on, and the count becomes 1. Before the page is built, a 95-step sequence is checked on all six outputs: counting up through 15 and around, down through 0 and around, loading 1010 while idle and in the middle of a count pulse, and CLR overriding LOAD.

Big circuit: pinch, scroll or tap + to zoom in, then drag to move around.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

4× D flip-flop with preset and clear: QA to QD, all clocked together
2× NAND + 1 AND: the direction latch (UP low means up, DOWN low means down) and the shared clock, UP AND DOWN
3× XNOR + 3 XOR + 2 AND + 1 NOT: the next count, Q + 1 or Q - 1
9× AND + 4 OR + 6 NOT: LOAD and CLR into each flip-flop's preset and clear, with CLR winning
6× AND + 2 NAND + 2 NOT: CO (low while the count is 15 and UP is low) and BO (low while the count is 0 and DOWN is low)

Step by step

Place inputs UP, DOWN, LOAD, CLR and A to D, and probes QA to QD, CO and BO.
Clock four D flip-flops together from UP AND DOWN, and let a NAND latch record which of UP and DOWN went low.
Give each flip-flop D = Q XOR T, where T is 1 when all lower bits are 1 (up) or all 0 (down); QA always toggles.
Wire LOAD and CLR to the presets and clears, and build CO and BO. Pulse UP low and high: the count goes up by one. Pulse DOWN: down by one.

74LS193 function table

CLR	LOAD	UP	DOWN	What happens
1	X	X	X	Clear: QA to QD all 0
0	0	X	X	Load: QA to QD take A to D at once
0	1	rising	1	Count up by one
0	1	1	rising	Count down by one
0	1	1	1	Hold

74LS193 pinout

Pin	Name	Pin	Name
1	B	16	VCC
2	QB	15	A
3	QA	14	CLR
4	DOWN	13	BO (active low)
5	UP	12	CO (active low)
6	QC	11	LOAD (active low)
7	QD	10	C
8	GND	9	D

X means the input does not matter; QA is the least significant bit. The behavior and the 16-pin pinout are from TI's SN74LS193 datasheet (SDLS074) and SN74HC193 datasheet (SCLS122D), checked 2026-10-25; the two share the pinout, and the 74HC193 runs from 2 V to 6 V. The 74LS192 in the same datasheet is the BCD version, counting 0 to 9.

You can also read the full theory in the lesson on synchronous counters. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the 74LS193 4-bit up/down counter in the lab →

Frequently asked

What does the 74LS193 do?

It is a 4-bit binary counter that counts up on rising edges of its UP input and down on rising edges of its DOWN input. It can be preset to any value with LOAD and cleared with CLR, and its CO and BO outputs let several chips count past 15.

How do you make a 74LS193 count down?

Hold UP high and pulse DOWN low then high: each rising edge of DOWN subtracts one. Counting up is the same with the inputs swapped.

How do you cascade two 74LS193 counters?

Connect CO of the first chip to UP of the second and BO of the first to DOWN of the second. The first chip's carry and borrow pulses then count the second chip up or down, giving 8 bits.

What is the difference between the 74LS192 and the 74LS193?

The 74LS192 counts in BCD, 0 to 9, and the 74LS193 in binary, 0 to 15. TI documents both in one datasheet with the same pinout.