CD4040: the 12-stage ripple binary counter chip, live

The CD4040 is a 12-stage ripple binary counter: each falling edge on its clock input adds one to a 12-bit count on outputs Q1 to Q12, so Q1 divides the clock by 2 and Q12 by 4,096. A high level on RESET clears every stage at once. The 74HC4040 has the same pinout. This live circuit is the whole chip.

TI's datasheet (CD4020B, CD4024B and CD4040B) puts it simply: "All counter stages are master-slave flip-flops. The state of a counter advances one count on the negative transition of each input pulse; a high level on the RESET line resets the counter to its all zeros state." It lists control counters, timers, frequency dividers and time-delay circuits as applications, for supplies from 3 V to 18 V. Ripple means each stage is clocked by the one before it: stage 1 toggles on the clock's falling edge, stage 2 when stage 1 falls from 1 to 0, and so on, so a change ripples up the chain one stage at a time. That makes the counter simple and the outputs perfect frequency dividers, but for a moment after an edge the count can read wrong while the ripple settles, so it is not the counter to decode states from at speed (a synchronous counter is). Each stage here is a master-slave D flip-flop with clear, wired as a toggle (D from its own Q'), the same chain as the 4-bit ripple counter, twelve long. The live chip opens with RESET high: set it to 0 and turn CLK on and off; Q1 changes each time CLK goes from 1 to 0. The full 4,096-count cycle, back to zero, has been checked on all twelve outputs, and every build of this page re-checks the first 70 counts and a reset in the middle of a count.

Big circuit: pinch, scroll or tap + to zoom in, then drag to move around.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

12× D flip-flop with clear: the stages Q1 to Q12, each toggling (D = its own Q') and clocked by the Q' of the stage before
1× NOT: the clock into stage 1, so the count advances on the falling edge

Step by step

Place inputs CLK and RESET, and probes Q1 to Q12.
Make each stage a toggle: a D flip-flop whose D is its own Q', with RESET on its clear.
Clock stage 1 from NOT CLK, and every later stage from the Q' of the stage before, so each toggles when the one below falls from 1 to 0.
Pulse RESET, then toggle CLK: Q1 changes on every falling edge, Q2 on every second, Q12 on every 2,048th.

CD4040 outputs and what they divide by

Output	Pin	Clock divided by	Changes every
Q1	9	2	1 clock
Q2	7	4	2 clocks
Q3	6	8	4 clocks
Q4	5	16	8 clocks
Q5	3	32	16 clocks
Q6	2	64	32 clocks
Q7	4	128	64 clocks
Q8	13	256	128 clocks
Q9	12	512	256 clocks
Q10	14	1,024	512 clocks
Q11	15	2,048	1,024 clocks
Q12	1	4,096	2,048 clocks

CD4040 pinout

Pin	Name	Pin	Name
1	Q12	16	VDD
2	Q6	15	Q11
3	Q5	14	Q10
4	Q7	13	Q8
5	Q4	12	Q9
6	Q3	11	RESET
7	Q2	10	Clock (input pulses)
8	VSS	9	Q1

"Changes every" counts falling clock edges. The pinout, the 3 V to 18 V range and the description are from TI's CD4040B datasheet (SCHS030D), checked 2026-10-25. TI's SN74HC4040 datasheet (SCLS160E) has the same pin positions with the outputs named QA to QL and the inputs CLK and CLR, for 2 V to 6 V.

You can also read the full theory in the lesson on counters. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the CD4040 12-stage binary counter in the lab →

Frequently asked

What does the CD4040 do?

It counts falling clock edges in binary on twelve outputs, Q1 to Q12, so each output is the clock divided by a power of two, from 2 at Q1 to 4,096 at Q12. A high RESET clears the count.

What is the CD4040 pinout?

Pin 1 Q12, 2 Q6, 3 Q5, 4 Q7, 5 Q4, 6 Q3, 7 Q2, 8 VSS, 9 Q1, 10 clock input, 11 RESET, 12 Q9, 13 Q8, 14 Q10, 15 Q11, 16 VDD.

How do you use a CD4040 as a frequency divider?

Feed the clock into pin 10 and hold RESET low. Output Qn is the clock divided by 2 to the n: a 32,768 Hz clock gives 16,384 Hz at Q1 and 8 Hz at Q12.

What is the difference between the CD4040 and the 74HC4040?

Same function and pin positions. The CD4040B runs from 3 V to 18 V; the 74HC4040 runs from 2 V to 6 V and is faster, and its datasheet names the outputs QA to QL.