CD4060: the 14-stage counter with a built-in oscillator, live

The CD4060 combines an oscillator with a 14-stage ripple binary counter. Each falling edge on its clock input, pin 11, adds one to the count, and ten stages come out on pins, Q4 to Q10 and Q12 to Q14, dividing the clock by 16 up to 16,384. A high RESET clears the count. Here the clock is a switch, CLKI.

TI's datasheet describes the CD4060B as "an oscillator section and 14 ripple-carry binary counter stages. The oscillator configuration allows design of either RC or crystal oscillator circuits." A high level on RESET resets the counter to all zeros and disables the oscillator, all stages are master-slave flip-flops, and the count advances on the falling edge of the clock. The oscillator is two inverting stages between pin 11 (the input, called phi I) and pins 9 and 10 (phi O and its inverse): the datasheet's typical RC circuit puts Rx from pin 10 to a timing node, Cx from that node to pin 9 and Rs from the node to pin 11, with Rs 2 to 10 times Rx, for a period of about T = 2.2 Rx Cx, and it also shows a crystal circuit. Fourteen stages divide hard: a 32,768 Hz clock comes out of Q14 at 2 Hz. This simulator is digital, so the oscillator itself is not modeled: CLKI is a switch, and each change from 1 to 0 counts one. The counter is fourteen toggling master-slave D flip-flops with clear, each clocked by the one before, as in the CD4040; Q1 to Q3 and Q11 stay inside, as on the chip, so after a reset Q4 first changes on the eighth pulse. The full 16,384-count cycle, back to zero, has been checked on all ten outputs, and every build of this page re-checks the first 70 counts and a reset in the middle of a count.

Big circuit: pinch, scroll or tap + to zoom in, then drag to move around.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

14× D flip-flop with clear: the stages, each toggling (D = its own Q'); Q1 to Q3 and Q11 have no pin, as on the chip
1× NOT: the clock into stage 1, so the count advances on the falling edge

Step by step

Place inputs CLKI and RESET, and probes for the pinned outputs Q4 to Q10 and Q12 to Q14.
Chain fourteen toggle stages (D flip-flops with D = Q'), the first clocked by NOT CLKI and each later one by the Q' of the stage before, all cleared by RESET.
Probe only the stages the chip brings out; Q1 to Q3 and Q11 stay internal.
Pulse RESET, then toggle CLKI: Q4 goes high after 8 falling edges and Q14 after 8,192.

CD4060 outputs and what they divide by

Output	Pin	Clock divided by	Changes every
Q4	7	16	8 clocks
Q5	5	32	16 clocks
Q6	4	64	32 clocks
Q7	6	128	64 clocks
Q8	14	256	128 clocks
Q9	13	512	256 clocks
Q10	15	1,024	512 clocks
Q12	1	4,096	2,048 clocks
Q13	2	8,192	4,096 clocks
Q14	3	16,384	8,192 clocks

CD4060 pinout

Pin	Name	Pin	Name
1	Q12	16	VDD
2	Q13	15	Q10
3	Q14	14	Q8
4	Q6	13	Q9
5	Q5	12	RESET
6	Q7	11	phi I (clock in)
7	Q4	10	phi O inverted
8	VSS	9	phi O

"Changes every" counts falling clock edges. The pinout, the RC circuit, the 3 V to 18 V range and the description are from TI's CD4060B datasheet (SCHS049C), checked 2026-10-25; it also notes that RC oscillator use is not recommended below 7 V when Rx is under 50 kilohms. TI's SN74HC4060 datasheet (SCLS161D) has the same pin positions, named QD to QN, CLKI, CLKO and CLR, for 2 V to 6 V.

You can also read the full theory in the lesson on counters. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the CD4060 14-stage counter and oscillator in the lab →

Frequently asked

What does the CD4060 do?

It is a 14-stage binary counter with its own oscillator. The oscillator, set by an RC network or a crystal, clocks the counter, and outputs Q4 to Q10 and Q12 to Q14 give that clock divided by 16 up to 16,384. A high RESET clears the count and stops the oscillator.

What is the CD4060 pinout?

Pin 1 Q12, 2 Q13, 3 Q14, 4 Q6, 5 Q5, 6 Q7, 7 Q4, 8 VSS, 9 phi O, 10 phi O inverted, 11 phi I (clock in), 12 RESET, 13 Q9, 14 Q8, 15 Q10, 16 VDD.

How do you set the CD4060 oscillator frequency?

With the datasheet's typical RC circuit (Rx from pin 10 to a timing node, Cx from the node to pin 9, Rs from the node to pin 11, Rs 2 to 10 times Rx), the period is about T = 2.2 Rx Cx, so the frequency is about 1 / (2.2 Rx Cx). Q14 then divides that by 16,384.

Why does the CD4060 have no Q1, Q2, Q3 or Q11 pins?

A 16-pin package has room for only ten outputs once power, RESET and the three oscillator pins are in place, so those four stages stay inside the chip. They still count; you just cannot connect to them.