Memory address register (MAR) and MDR: a live circuit

The memory address register (MAR) holds the address of the memory location being read or written, so the address stays put while the bus moves on to carry data. Its partner, the memory data register (MDR), holds the word read from that location. This live circuit has a 2-bit MAR, a 4-word memory and a 4-bit MDR, all fed from one 4-bit bus.

In a simple CPU the address and the data take turns on one shared bus. First the address goes into the MAR: the program counter's value during an instruction fetch, or an operand's address during a load or store. From then on the memory sees that address on its address lines, and the bus is free for data: a write stores the bus value at the MAR's address, and a read puts the addressed word on the memory's output, where the MDR captures it on the next clock edge. Here BUS3 to BUS0 is the bus. With LDMAR high, a rising edge of CLK loads the low two bus bits into the MAR; with WR high, it writes the bus into the word the MAR points at; with LDMDR high, it copies that word, shown on M3 to M0, into the MDR. The MAR is two D flip-flops with a load choice in front, the memory is four of the 4-bit registers with load plus a 2-to-4 decoder for the write enables and four 4:1 multiplexers for reading (the same build as the register file), and the MDR is one more 4-bit register. Everything starts unknown, as real registers and RAM do at power-on. The live circuit opens with LDMAR high and the bus at 0000: turn CLK on and off to load address 00, set LDMAR to 0, put a value on the bus, set WR to 1 and pulse CLK to store it. Before the page is built, an 84-step sequence is checked on the MAR, M and the MDR: writing four words, reading them back in a different order through the MDR, the bus changing while the MAR and MDR hold, and overwriting a word.

Big circuit: pinch, scroll or tap + to zoom in, then drag to move around.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

2× D flip-flop + 4 AND + 2 OR + 1 NOT: the MAR, loaded from BUS1 BUS0 when LDMAR is high
4× 4-bit register with load: the memory words, each written when WR is high and the MAR points at it
8× AND + 2 NOT: decoding the MAR into the four write enables, gated by WR
4× 4:1 multiplexer: reading the addressed word onto M3 to M0
1× 4-bit register with load: the MDR, loaded from M when LDMDR is high

Step by step

Place inputs BUS3 to BUS0, LDMAR, WR, LDMDR and CLK, and probes MAR1, MAR0, M3 to M0 and MDR3 to MDR0.
Build the MAR: two D flip-flops on CLK whose D is BUS when LDMAR is 1 and their own Q when it is 0.
Build the memory: four 4-bit registers on the bus, each loaded when WR is 1 and the MAR decodes to its number, read through 4:1 multiplexers selected by the MAR.
Add the MDR: a 4-bit register that loads M when LDMDR is 1. Load an address, write a value, load another address, then read the first one back.

What each control does on a clock edge

Control high	On the rising edge of CLK
LDMAR	MAR takes BUS1 BUS0, the address
WR	the word at the MAR's address takes BUS3 to BUS0
LDMDR	MDR takes the word at the MAR's address
none	nothing changes

The memory is read all the time: M3 to M0 always show the word at the MAR's address, and the MDR keeps its copy until the next LDMDR. Real memories are far wider and deeper, but the MAR and MDR play the same roles. Small CPUs, like the one in digiwleea's course, often let the program counter drive the address lines directly and fold the MAR away.

You can also read the full theory in the lesson on RAM. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the memory address register (MAR) and MDR in the lab →

Frequently asked

What is the memory address register?

A register that holds the address of the memory location the CPU is reading or writing right now. Memory takes its address from the MAR, so the address stays steady for the whole access while the bus carries other values.

What is the difference between the MAR and the MDR?

The MAR holds where in memory to read or write (an address); the MDR holds what is being read or written (the data). An access loads the MAR first, then moves the data through the MDR.

What is the difference between the program counter and the MAR?

The program counter holds the address of the next instruction. The MAR holds whatever address memory is using right now: during an instruction fetch it gets a copy of the program counter, and during a load or store it gets the operand's address instead.

Why does a CPU need a memory address register?

Because the address has to stay on memory's address lines for the whole access, while the shared bus is needed for other things, such as the data itself. Latching the address in the MAR frees the bus.