Hardwired control unit: fetch and execute, live
A hardwired control unit produces a CPU's control signals with fixed logic: a step counter says where the processor is in the instruction cycle, and gates combine the step with the opcode to raise the right signals. In this one, step T = 0 is fetch (IR_LD and PC_INC) and step T = 1 is execute, where the opcode OP1 OP0 picks exactly one of ACC_LD, ACC_ADD, MEM_WR or PC_LD.
Every control signal in a CPU is a yes-or-no question: load the instruction register now? Write memory now? In a hardwired design each answer is a logic expression of the current step and the instruction. Here the step is one flip-flop that toggles every clock, so the machine alternates fetch and execute; RST forces fetch. During fetch the instruction register loads the instruction at the program counter's address and the PC moves on. During execute a 2-to-4 decoder on the opcode, ANDed with T, raises one signal: LOAD (00) loads the accumulator from memory, ADD (01) adds into it, STORE (10) writes it to memory, and JMP (11) loads the PC. A microprogrammed control unit gets the same signals differently: it stores them as words in a small control memory and steps through them, which is slower but easier to change, while hardwired logic is faster and is what most simple and RISC processors use. Real machines need more steps (digiwleea's course CPU uses several per instruction), but each extra step is just another state and more gates of the same kind.
Open this circuit in the lab →
What you need
- 1× D flip-flop: the step T
- 1× AND: next step = NOT T AND NOT RST (toggle, or back to fetch on reset)
- 4× NOT: NOT T (which is also IR_LD and PC_INC), NOT RST, NOT OP1, NOT OP0
- 4× AND: the 2-to-4 opcode decoder
- 4× AND: each decoded line ANDed with T, so it acts only in the execute step
Step by step
- Place a clock
CLK, inputsRST,OP1andOP0, one D flip-flop for the step, and probes for T and the six control signals. - Step counter: feed NOT T AND NOT RST back into the flip-flop's D, so T alternates 0, 1, 0, 1 and returns to 0 on reset.
- Fetch signals: IR_LD and PC_INC are simply NOT T, active in step 0.
- Execute signals: decode OP1 OP0 with four ANDs (one per opcode) and AND each with T. Turn RST off and watch the signals take turns as T toggles; change the opcode to pick a different execute signal.
Fetch and execute, step by step
| Clock edge | RST | Opcode | T | Step | Active signals |
|---|---|---|---|---|---|
| 1 | 1 | 00 (LOAD) | 0 | fetch | IR_LD, PC_INC |
| 2 | 0 | 00 (LOAD) | 1 | execute | ACC_LD |
| 3 | 0 | 00 (LOAD) | 0 | fetch | IR_LD, PC_INC |
| 4 | 0 | 01 (ADD) | 1 | execute | ACC_ADD |
| 5 | 0 | 01 (ADD) | 0 | fetch | IR_LD, PC_INC |
| 6 | 0 | 10 (STORE) | 1 | execute | MEM_WR |
| 7 | 0 | 10 (STORE) | 0 | fetch | IR_LD, PC_INC |
| 8 | 0 | 11 (JMP) | 1 | execute | PC_LD |
| 9 | 0 | 11 (JMP) | 0 | fetch | IR_LD, PC_INC |
| 10 | 0 | 01 (ADD) | 1 | execute | ACC_ADD |
| 11 | 1 | 01 (ADD) | 0 | fetch | IR_LD, PC_INC |
| 12 | 0 | 10 (STORE) | 1 | execute | MEM_WR |
| 13 | 0 | 10 (STORE) | 0 | fetch | IR_LD, PC_INC |
This is the exact run checked before the page is built, on T and all six control signals after each of the 13 clocks: each instruction gets a fetch and an execute step, and a reset during execute (edge 11) sends the unit straight back to fetch. The live circuit opens held in reset, because the step flip-flop starts in an unknown state. Hardwired control is traditionally the RISC choice and microcode the CISC one; see RISC vs CISC.
You can also read the full theory in the lesson on the control unit. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.
More builds: Registers and counters
All 246 build guides, by topic
Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.
Open the Hardwired control unit in the lab →Frequently asked
What is a hardwired control unit?
A control unit whose control signals come from fixed logic gates: a step counter tracks the stage of the instruction cycle, and combinational logic combines the step with the opcode to produce each signal.
What is the difference between hardwired and microprogrammed control units?
A hardwired unit computes the control signals with gates, which is fast but fixed. A microprogrammed unit stores them as microinstructions in a control memory and steps through them, which is slower but easier to change or extend.
What does the control unit do in a CPU?
It reads the current instruction and the step of the instruction cycle and raises the signals that make the rest of the processor act: load a register, add, write memory, change the program counter.
Why does the control unit need a step counter?
Most instructions take several clock cycles, such as fetch, then decode and execute, and different signals are needed in each. The step counter (or a state machine) says which cycle it is.