8-bit register: store a byte with a load enable, live
An 8-bit register stores one byte: eight D flip-flops on one clock, each with a 2-to-1 multiplexer in front, so that when LD is 1 the next clock edge copies I7 to I0 into Q7 to Q0 all at once, and when LD is 0 every flip-flop gets its own output back and the byte holds.
It is the 4-bit register with parallel load made twice as wide: the same multiplexer per bit, one shared NOT for LD, and one clock for all eight flip-flops, so the byte changes in a single step. Registers like this are the working memory of a CPU. An 8-bit processor has an accumulator, an instruction register and often general-purpose registers, each a byte wide and each with its own load signal that the control logic raises for exactly one clock when that register should take the value on the bus. Everything else in the register's life is holding. Because a byte is two hex digits, the table below also shows Q in hex, the way registers usually appear in a debugger. With tri-state outputs added so that several registers can share one bus, this is the job of a chip such as the 74HC374; four of the smaller registers with read and write logic make a register file.
Open this circuit in the lab →
What you need
- 8× D flip-flop: one per bit, all on the same clock
- 8× AND: load path: I AND LD
- 8× AND: hold path: Q AND NOT LD
- 8× OR: join the two paths into each D input (with the ANDs, a 2-to-1 mux per bit)
- 1× NOT: NOT LD, shared by all eight bits
Step by step
- Place a clock
CLK, a load inputLD, data inputsI7toI0and eight D flip-flops, all clocked by CLK. - For each bit, AND the data input with LD (the value to load) and AND the flip-flop's own Q with
NOT LD(the value to keep). - OR the two into the flip-flop's D input, so D = I when LD = 1 and D = Q when LD = 0.
- Probe
Q7toQ0. With LD on, set a byte on the inputs and clock it in; turn LD off and the register holds while the inputs change.
Load and hold sequence
| Clock edge | LD | I7..I0 | Q7..Q0 | Q in hex |
|---|---|---|---|---|
| 1 | 1 | 10100101 | 10100101 | A5 |
| 2 | 0 | 01011010 | 10100101 | A5 |
| 3 | 0 | 11111111 | 10100101 | A5 |
| 4 | 1 | 11111111 | 11111111 | FF |
| 5 | 0 | 00001111 | 11111111 | FF |
| 6 | 1 | 00000000 | 00000000 | 00 |
| 7 | 1 | 00111100 | 00111100 | 3C |
| 8 | 1 | 11000011 | 11000011 | C3 |
| 9 | 0 | 10000001 | 11000011 | C3 |
| 10 | 0 | 01111110 | 11000011 | C3 |
This is the exact run checked before the page is built: all eight outputs after each of the 10 clocks. With LD at 0 the inputs change freely (edges 2, 3, 5, 9 and 10) and Q keeps its byte; with LD at 1 the whole byte is replaced at once, including two loads in a row on edges 6, 7 and 8.
You can also read the full theory in the lesson on the register bit. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.
More builds: Registers and counters
All 246 build guides, by topic
Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.
Open the 8-bit register with load in the lab →Frequently asked
What is an 8-bit register?
A circuit that stores one byte: eight flip-flops sharing a clock and a load control. When load is 1, the next clock edge writes all eight input bits at once; when load is 0, the stored byte stays put.
How many flip-flops are in an 8-bit register?
Eight, one per bit. This one also has a 2-to-1 multiplexer per bit (two ANDs and an OR) and a single NOT for the load signal, so 8 flip-flops and 25 gates.
What is a register used for in a CPU?
Holding the values the processor is working on right now: the accumulator, the instruction being executed, addresses and intermediate results. Each register loads from the data bus only when the control logic raises its load signal.
What is the difference between a register and memory?
A register is a handful of flip-flops inside the processor, read and written in a single clock. Memory (RAM) holds many words at addresses and is reached through an address and a read or write cycle, so it is much bigger but slower to use.