Instruction register and decoder: a live CPU circuit

The instruction register (IR) holds the instruction a CPU is executing. This 8-bit IR loads a byte from the bus on a clock edge while LDI is 1 and holds it otherwise; its low four bits are the operand (A3 to A0) and its high four bits, the opcode, are decoded into one control line per instruction: LOAD, ADD, STORE, SUB, JMP, JZ, OUT and HALT.

The opcodes are the ones digiwleea's course assembler uses: 1 LOAD, 2 ADD, 3 STORE, 4 SUB, 5 JMP, 6 JZ, 7 OUT and F HALT, with the operand as a 4-bit address, so 0x25 means ADD the value at address 5. During a fetch the program counter addresses memory, the instruction byte arrives on the bus, and the control unit raises LDI for one clock so the IR captures it. From then on the byte stays put while the bus is used for data, and the decoder turns the opcode into exactly one active line, which the control unit uses to steer the rest of the processor: LOAD and ADD select the accumulator's input, JMP loads the program counter, and so on. Each line is a 4-input AND of the opcode bits or their complements, the same idea as a 4-to-16 decoder keeping only the eight rows the instruction set uses; the unused codes 0 and 8 to E light no line at all. The register half is the 8-bit register with load.

Open this circuit in the lab →

What you need

• 8× D flip-flop: the instruction byte, all on one clock
• 16× AND: load path (I AND LDI) and hold path (Q AND NOT LDI) for each bit
• 8× OR: joining the two paths into each D input
• 5× NOT: NOT LDI, and the four complemented opcode bits
• 24× AND: the decoder: three 2-input ANDs per opcode line, eight lines

Step by step

1. Place a clock CLK, a load input LDI, bus inputs I7 to I0 and eight D flip-flops on CLK.
2. For each bit, choose between the bus bit (when LDI is 1) and the flip-flop's own output (when LDI is 0) with two ANDs and an OR into D.
3. Probe the low four flip-flops as the operand A3 to A0.
4. Invert the four opcode bits once, then for each opcode AND together the four bits or complements that match its code: LOAD is 0001, so LOAD = NOT Q7 AND NOT Q6 AND NOT Q5 AND Q4. Load a few instruction bytes and watch one line light at a time.

Load, hold and decode

This is the exact run checked before the page is built, on all eight decoded lines and the four operand bits after each of the 12 clocks: every opcode loaded once, the bus changing while LDI is 0 (edges 4, 5 and 10) without touching the IR, and an unused opcode (9) that lights no line. The live circuit opens loading 0x13, LOAD 3. How these bytes are written as LOAD, ADD and STORE: assembly vs machine code.

You can also read the full theory in the lesson on the instruction register. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

More builds: Registers and counters

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Frequently asked

What is the instruction register?

The CPU register that holds the instruction currently being executed. It is loaded from memory during the fetch step and then decoded to control the rest of the processor.

What does the instruction decoder do?

It turns the instruction's opcode bits into control signals, here one line per instruction, so that the right parts of the CPU act: for example ADD makes the accumulator take the adder's output.

What is the difference between the opcode and the operand?

The opcode says what to do (LOAD, ADD, JMP and so on) and the operand says what to do it with, usually an address or a value. In this 8-bit format the high nibble is the opcode and the low nibble the operand.

What is the difference between the instruction register and the program counter?

The program counter holds where the next instruction is, an address. The instruction register holds the instruction itself, after it has been fetched from that address.