RISC vs CISC: two ways to design an instruction set
RISC (reduced instruction set computer) and CISC (complex instruction set computer) are two philosophies for designing a processor's instruction set. RISC keeps instructions few, simple and usually fixed in length, and only loads and stores touch memory, so each instruction is easy to decode and pipeline. CISC offers richer instructions, often of variable length, that can operate on memory directly, so a program needs fewer of them. David Patterson coined the acronym RISC at Berkeley for the RISC-1 chip, after he and David Ditzel published "The Case for the Reduced Instruction Set Computer" in 1980; RISC-II became the foundation of Sun's SPARC, and John Hennessy's MIPS appeared at Stanford around the same time. Patterson and Hennessy shared the 2017 Turing Award. x86 is the best-known CISC instruction set; Arm and the open, royalty-free RISC-V are RISC. Today the question is mostly about the instruction set, not the hardware underneath: fast CPUs of both kinds pipeline and reorder simple internal operations.
What each approach is good at
RISC's simple, regular instructions make decoding cheap and pipelining natural, which is why it suits small, low-power cores and teaching, and why RISC-V and Arm cover everything from microcontrollers to servers. CISC's dense instructions do more per byte of code, and x86 has kept decades of software running on one instruction set. In practice the hardware has converged: Intel's documentation for its P6-family processors already described splitting x86 instructions into micro-ops that execute on an out-of-order core.
Where digiwleea fits
digiwleea's course CPU is an 8-bit accumulator machine you build from transistors up, and it sits outside both labels in an instructive way. Every instruction is one byte, a 4-bit opcode and a 4-bit address, which is as regular as RISC gets, and its hardwired control unit decodes it in one step. But ADD and SUB read their operand straight from memory into the accumulator, as the early accumulator machines did, rather than loading registers first. The capstone runs a stored LOAD, ADD, STORE, HALT program, and Act IV builds the parts behind SUB, JMP, JZ and OUT. Compare the hardwired unit with the microprogrammed one, read machine code and microcode, and step real RISC programs in Ripes or RARS.
RISC and CISC side by side
| RISC | CISC | |
|---|---|---|
| Instructions | Fewer, simpler, usually fixed length | More, richer, often variable length |
| Memory access | Load-store: arithmetic only on registers | Arithmetic can read or write memory directly |
| Registers | Many general-purpose registers | Traditionally fewer |
| Control unit | Traditionally hardwired | Traditionally microcoded |
| Examples | RISC-V, Arm, MIPS, SPARC | x86 |
The line has blurred: Intel's documentation for its P6-family processors already describes breaking x86 instructions into simple micro-ops that an out-of-order core executes, a RISC-like engine behind a CISC instruction set.
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More comparisons: Digital logic concepts compared
See for yourself: build a logic gate from transistors in the simulator, then follow the path from sand to an 8-bit CPU.
Open the digiwleea lab →Frequently asked
What is the main difference between RISC and CISC?
RISC uses a small set of simple, usually fixed-length instructions and only touches memory with loads and stores. CISC uses a larger set of richer, often variable-length instructions that can operate on memory directly.
Is x86 RISC or CISC?
x86 is a CISC instruction set. Intel's documentation for its P6-family processors (the Pentium Pro and Pentium II generation) describes breaking x86 instructions into simpler micro-ops that an out-of-order core executes.
Is ARM RISC or CISC?
Arm is a RISC architecture, as are RISC-V, MIPS and SPARC.
Who invented RISC?
David Patterson coined the term at UC Berkeley for the RISC-1 chip, following his 1980 paper with David Ditzel, "The Case for the Reduced Instruction Set Computer". John Hennessy's MIPS project at Stanford developed the same ideas, and the two shared the 2017 Turing Award.
Is RISC-V free to use?
Yes. RISC-V International describes RISC-V as an open, royalty-free instruction set standard that anyone can build on.
What do RISC and CISC stand for?
RISC stands for reduced instruction set computer and CISC for complex instruction set computer. RISC examples are ARM, RISC-V and MIPS; the classic CISC example is x86.
What are the advantages and disadvantages of RISC and CISC?
RISC instructions are simple and uniform, which makes them easy to decode and pipeline, but a program needs more of them. CISC instructions do more each and give denser code, but they vary in length and work, which makes the decoder more complex.
What is an instruction set architecture (ISA)?
The contract between software and hardware: the instructions a processor understands, its registers, how it addresses memory and how instructions are encoded in binary. RISC and CISC are two styles of ISA; x86, ARM and RISC-V are particular ISAs.