Active high vs active low: which level means on
Every control signal has an asserted level, the level at which it does its job. An active-high signal is asserted when it is 1 (HIGH): an active-high enable turns a chip on when it is 1. An active-low signal is asserted when it is 0 (LOW): an active-low reset resets the chip when it is pulled to 0 and does nothing while it is 1. Both carry the same information; they differ only in which level means on. When you read a pin name, first check its asserted level: a bar over the name, a trailing N, _n or #, or a small bubble on a schematic pin all mean active low.
Why both exist
Active high is the natural reading and the usual choice inside a design. Active low is common on chip pins for practical reasons. TTL outputs can sink far more current to ground than they can source from the supply, so lighting an LED or a common-anode display by pulling an output LOW works better. Shared lines such as interrupts and resets are often open-collector or open-drain, where any device can pull the line LOW and a pull-up holds it HIGH otherwise, so LOW has to mean asserted. And a reset that is asserted while the power supply is still at 0 V holds the circuit in reset until the supply is up. In gate terms, a bubble is just a NOT: by De Morgan's law a NAND is an OR with active-low inputs, which is why designers draw it that way when the inputs are active low.
Active-low pins you can try live
Several live chips in digiwleea have active-low pins. The 74LS138 decoder pulls the selected output LOW while the other seven stay HIGH, and decodes only when G1 = 1 and the active-low enables G2A and G2B are 0. The 74LS47 drives a common-anode display with active-low outputs, so a LOW output lights its segment. The 7474 D flip-flop has an active-low preset and clear, and the NAND SR latch sets and resets on LOW inputs. Each one runs on the same simulator you use to build gates from transistors and work up to a CPU.
Active high and active low side by side
| Active high | Active low | |
|---|---|---|
| Asserted (on) at | 1, HIGH | 0, LOW |
| Idle level | LOW | HIGH |
| Written as | Plain name, e.g. EN | Bar, N, _n, # or a bubble, e.g. RST_N |
| Common for | Signals inside a design, most enables | Resets, chip selects, interrupts, LED and display drivers |
| Live example | 74LS138 enable G1 | 74LS138 outputs, enables G2A and G2B |
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More comparisons: Digital logic concepts compared
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Open the digiwleea lab →Frequently asked
What does active low mean?
An active-low signal does its job when it is 0 (LOW) and is inactive when it is 1 (HIGH). For example, an active-low reset resets the circuit while it is held LOW.
How is an active-low signal written?
With a bar over the name, a slash or asterisk, a trailing N, _n, _b or #, or a small circle (bubble) where the signal meets the gate or chip on a schematic. For example RESET with a bar, RESET_N or RST#.
Why are so many chip pins active low?
TTL outputs sink current much better than they source it, so LOW is the strong state for driving loads; shared open-collector or open-drain lines can only be pulled LOW by each device; and an active-low reset is asserted while the supply is still at 0 V during power-up.
Is active low the same as negative logic?
No. Active low describes one signal: which level asserts it. Negative logic is a convention for a whole system in which LOW stands for 1 and HIGH for 0. Most designs use positive logic and still have some active-low signals.
Is a NAND gate active low?
A NAND has an active-low output if you read it as an AND: its output goes LOW only when all inputs are HIGH. By De Morgan's law it is also an OR with active-low inputs, which is why it can be drawn either way.