PAL vs PLA: which array is programmable, and why it matters
A PLA (programmable logic array) and a PAL (programmable array logic) are both chips that implement sum-of-products logic with two arrays: an AND array that forms product terms from the inputs and their complements, and an OR array that adds product terms into outputs. The difference is which array you program. In a PLA both are programmable: you choose the inputs of every product term and which terms feed every output, so one term can be shared by several outputs. In a PAL only the AND array is programmable; the OR array is fixed, so each output ORs its own fixed group of product terms. Texas Instruments coined the term programmable logic array for its mask-programmed TMS2000 in 1970, and Monolithic Memories introduced the PAL in March 1978. In one line: a PLA programs both the AND and the OR array, so it is more flexible; a PAL programs only the AND array, so it is simpler, and typically faster and cheaper.
What each one is good at
A PLA is good when several outputs need the same product terms: a term is built once and fed to every output that uses it, and an output can collect as many terms as the chip has. The price is a second programmable array in the signal path, which takes area and adds delay. A PAL is good when each output needs only a handful of terms: with the OR array fixed there are fewer programmable connections, which made PALs simpler to program and typically faster and cheaper, and they were widely used to replace groups of small logic chips. Early PALs used one-time programmable fuses; Lattice's GAL (generic array logic, 1985) made the same idea electrically erasable and pin-compatible, and later CPLDs put many PAL-like blocks on one chip.
Try the PLA live, and the rest of the family
The programmable logic array example is a live, engine-checked PLA: three inputs, four product terms and two outputs, F1 = AB' + AC + A'BC' and F2 = AC + BC, with the shared term AC built once. The same two functions on a PAL are worked through below. A ROM is the third member of the family: its AND array is fixed as a full decoder of every input combination and its OR array is programmable, as in the full adder from a decoder and OR gates; see ROM vs RAM and the ROM and PLA lesson. FPGAs took a different route, look-up tables instead of AND and OR arrays: how an FPGA works and FPGA vs ASIC. To find the minimal sum of products to program into either array, use the truth table to expression converter.
PAL and PLA side by side
| PLA | PAL | ROM (for comparison) | |
|---|---|---|---|
| AND array | Programmable | Programmable | Fixed (decodes every input combination) |
| OR array | Programmable | Fixed | Programmable |
| Product terms shared between outputs | Yes | No, each output has its own | Yes, every minterm is available |
| Terms per output | Any of the chip's terms | A fixed number per output | All minterms |
| Flexibility | Highest | Lower | Any function, but grows as 2^n |
| Speed and cost | Two programmable arrays: more delay and area | One programmable array: typically faster and cheaper | Simple, but large for many inputs |
| Introduced | TI TMS2000, 1970 (mask-programmed) | Monolithic Memories, March 1978 | Not covered here |
The same two functions in a PLA and in a PAL
Take F1 = AB' + AC + A'BC' and F2 = AC + BC, the functions of the live PLA example.
| PLA | PAL | |
|---|---|---|
| Product terms built | 4: AB', AC, A'BC', BC | 5: AB', AC, A'BC' for F1, and AC, BC for F2 |
| AC | Built once, fed to both outputs | Built twice, once in each output's group |
| F1 | OR of terms 1, 2, 3 | Its own 3 terms (fits if its OR gate has at least 3 inputs) |
| F2 | OR of terms 2, 4 | Its own 2 terms |
A PAL output that needs more terms than its fixed OR gate has must be split, for example by feeding one output back in as an input to another.
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More comparisons: Digital logic concepts compared
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Open the digiwleea lab →Frequently asked
What is the difference between PAL and PLA?
In a PLA both the AND array and the OR array are programmable. In a PAL only the AND array is programmable and the OR array is fixed, so each output ORs its own group of product terms and terms cannot be shared between outputs.
Which is faster, PAL or PLA?
A PAL is typically faster, because the signal passes through one programmable array instead of two. A PLA's programmable OR array adds delay and area in exchange for flexibility.
What is PAL in digital electronics?
Programmable array logic: a chip with a programmable AND array feeding a fixed OR array, used to implement sum-of-products logic. Monolithic Memories introduced it in 1978; parts such as the PAL16L8 (8 combinational outputs) and PAL16R8 (8 registered outputs) replaced many small logic chips.
What is a PLA in digital electronics?
A programmable logic array: a programmable AND array that forms product terms and a programmable OR array that combines them into outputs, so any set of sum-of-products functions that fits the chip's terms can be implemented, with terms shared between outputs.
What is GAL?
Generic array logic, introduced by Lattice Semiconductor in 1985: a PAL-style device with an electrically erasable (EEPROM) array, so it can be reprogrammed, built as a pin-compatible replacement for one-time programmable PALs.
How is a ROM different from a PLA and a PAL?
A ROM has a fixed AND array that decodes every input combination and a programmable OR array. A PLA programs both arrays, and a PAL programs only the AND array.