Programmable logic array (PLA): example circuit, live
A programmable logic array (PLA) implements several sum-of-products functions at once: an AND plane forms product terms from the inputs and their complements, and an OR plane adds chosen terms into each output. Here three inputs and four product terms make F1 = AB' + AC + A'BC' and F2 = AC + BC.
In a PLA chip both planes are programmable: you choose which inputs (true or complemented) feed each AND term and which terms feed each OR output. The live circuit is one such programming, with every programmed connection drawn as a wire. The point of the AND plane is sharing: the term AC appears in both F1 and F2 but is built once, so two outputs need only four product terms. A decoder plus OR gates, which is how a ROM computes logic, would instead decode all eight input combinations. The variant with a fixed OR plane and only the AND plane programmable is called a PAL: see PAL vs PLA. The circuit starts at A = B = C = 0, where both outputs are 0; all eight rows of both outputs are checked before the page is built.
Open this circuit in the lab →
What you need
- 3× NOT: complemented inputs A', B', C' (the input buffers of the AND plane)
- 5× AND: AND plane: P1 = AB', P2 = AC, P3 = BC, and P4 = A'BC' from two 2-input ANDs
- 3× OR: OR plane: F1 = P1 + P2 + P4 from two 2-input ORs, F2 = P2 + P3
Step by step
- Write each output as a sum of products, for example from a K-map:
F1 = AB' + AC + A'BC'andF2 = AC + BC. - List the distinct product terms:
P1 = AB',P2 = AC,P3 = BC,P4 = A'BC'. AC is shared, so there are four, not five. - Build the AND plane: invert A, B and C, then one AND per product term.
- Build the OR plane: OR P1, P2 and P4 into
F1, and P2 and P3 intoF2. - Sweep A B C from 000 to 111 and compare each output with the table below.
PLA product terms and outputs
| A | B | C | P1 = AB' | P2 = AC | P3 = BC | P4 = A'BC' | F1 | F2 |
|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 |
Each output is the OR of its programmed product terms: F1 of P1, P2 and P4, F2 of P2 and P3. A PLA is usually specified by a programming table with one row per product term, marking which inputs appear true (1), complemented (0) or not at all (-), and which outputs use the term: here P1 is 1 0 -, P2 is 1 - 1, P3 is - 1 1 and P4 is 0 1 0.
You can also read the full theory in the lesson on ROM and PLA. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.
More builds: Selecting, routing and decoding
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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.
Open the programmable logic array (PLA) in the lab →Frequently asked
What is a programmable logic array?
A PLA is a programmable logic device with an AND plane that forms product terms from the inputs and their complements and an OR plane that combines those terms into the outputs. Both planes are programmable, so it implements several sum-of-products functions at once.
What is the difference between a PLA and a PAL?
In a PLA both the AND plane and the OR plane are programmable. In a PAL only the AND plane is programmable and each output ORs a fixed group of product terms, which makes a PAL faster and simpler but less flexible.
What is the difference between a PLA and a ROM?
A ROM decodes every input combination (a full decoder as its AND plane) and stores the output for each one, so it can implement any function but grows as 2 to the n. A PLA builds only the product terms the functions need, so it is smaller when the functions minimize well.
Why does sharing product terms matter in a PLA?
A PLA has a fixed number of product terms. A term used by several outputs, like AC here, is built once in the AND plane and connected to each OR, so minimizing the functions together rather than one at a time can save terms.