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1-to-32 demultiplexer using 1-to-8 demultiplexers, live

A 1-to-32 demultiplexer can be built from four 1-to-8 demultiplexers and one 1-to-4 demultiplexer. S4 and S3 drive the 1-to-4 demux, which sends D to the data input of one 1-to-8 demux; S2, S1 and S0 drive all four 1-to-8 demuxes, and the one that received D passes it to the selected output.

The five select bits split into a group and a position. The high two bits S4 S3 choose one of four groups of eight outputs, and the low three bits S2 S1 S0 choose the output inside the group, so output number 8 x (S4 S3) + (S2 S1 S0) gets D and the other 31 stay 0. With S4 S3 S2 S1 S0 = 10110 (22), the 1-to-4 demux sends D to its output 2, the third 1-to-8 demux, which drives its output 6, and 16 + 6 = 22, so Y22 = D. The three 1-to-8 demuxes that did not get D see a 0 on their data input, so all their outputs stay 0 whatever S2 S1 S0 are. This is the mirror image of the 32-to-1 mux using 8-to-1 muxes: there the group is chosen at the end, here at the start. If only 1-to-8 demuxes are available, a fifth one can replace the 1-to-4, with S4 S3 on two of its selects, the third tied to 0, and four outputs unused. The blocks are the verified gate-level 1-to-8 demultiplexer and 1-to-4 demultiplexer, saved as parts; open the circuit in the lab to look inside.

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Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

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To cite it: digiwleea, “1-to-32 demultiplexer from 1-to-8 demuxes”, https://digiwleea.wleeaf.dev/tools/build/demultiplexer-1to32-from-1to8/

What you need

Step by step

  1. Place a data input D, selects S4 to S0 and probes Y0 to Y31.
  2. Wire D into a 1-to-4 demux with S4 and S3 as its selects.
  3. Connect each of its four outputs to the data input of its own 1-to-8 demux, and S2, S1 and S0 to the selects of all four.
  4. The 1-to-8 outputs, in order, are Y0 to Y31. Set S4 to S0 to any number from 0 to 31 with D = 1: only that output is 1. Turn D off and every output is 0.

Which demux drives which output

S4 S31-to-8 demux that gets DS2 S1 S0Output that equals D
00first000 to 111Y0 to Y7
01second000 to 111Y8 to Y15
10third000 to 111Y16 to Y23
11fourth000 to 111Y24 to Y31

Before the page is built, all 64 rows (D = 0 and D = 1 for each of the 32 select values) are checked on the live circuit, every one of the 32 outputs on every row, so D reaches only the selected output. Tie D to 1 and the same circuit is a 5-to-32 decoder. Smaller trees: the 1-to-16 demultiplexer and the 4-to-16 decoder from 2-to-4 decoders.

You can also read the full theory in the lesson on encoders and demultiplexers. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

More builds: Selecting, routing and decoding

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the 1-to-32 demultiplexer from 1-to-8 demuxes in the lab →

Frequently asked

How do you design a 1 to 32 demux using 1 to 8 demuxes?

Use a 1-to-4 demux on S4 S3 to send D to one of four 1-to-8 demuxes, and drive the selects of all four 1-to-8 demuxes with S2 S1 S0. Their 32 outputs, in order, are Y0 to Y31.

How many 1 to 8 demuxes are needed for a 1 to 32 demux?

Four, plus a 1-to-4 demux to choose among them. Using 1-to-8 demuxes only, a fifth one can do the choosing with two of its select lines, leaving four of its outputs unused.

How many select lines does a 1 to 32 demultiplexer have?

Five, because 2^5 = 32. The select value S4 S3 S2 S1 S0 is the number of the output that receives D.

How many 1 to 4 demuxes make a 1 to 32 demux?

Eleven: one 1-to-2 stage is needed on top, so with 1-to-4 demuxes only, one demux (using one select line) feeds two, those feed eight, and the eight drive the 32 outputs. That is 1 + 2 + 8 = 11.

What is a 1 to 32 demux used for?

Routing one signal to one of 32 places, for example a write enable to one of 32 registers or memory rows. Tied to D = 1, it is a 5-to-32 decoder, the address decoder for 32 locations.