2-to-4 decoder using NOR gates only, live
A 2-to-4 decoder can be built from six NOR gates: two NORs with their inputs tied make A1' and A0', and four more give the outputs, Y0 = NOR(A1, A0), Y1 = NOR(A1, A0'), Y2 = NOR(A1', A0) and Y3 = NOR(A1', A0'). Exactly one output is 1, the one numbered A1 A0.
Each output of a 2-to-4 decoder is one minterm: Y0 = A1' A0', Y1 = A1' A0, Y2 = A1 A0' and Y3 = A1 A0. A NOR gate is an AND of complements, NOR(x, y) = x' y' by De Morgan's law, so each output is a NOR of the opposite literals. Y0 needs A1' A0', which is NOR(A1, A0), straight from the inputs. Y3 needs A1 A0, which is NOR(A1', A0'), so it takes both complements. Y1 and Y2 take one of each. The complements come from NOR gates with both inputs tied together, since NOR(x, x) = x', so the whole decoder uses one gate type, six gates in all. With an active-low enable E', every output gate becomes a 3-input NOR with E' as the third input: while E' = 1 all outputs stay 0. The AND-gate version is the 2-to-4 decoder from logic gates; the NAND-gate version gives active-low outputs, NAND(A1', A0') and so on, where the selected output is the one that goes to 0. More NOR-only circuits: every gate from NOR, the half adder and the full adder from NOR gates.
Open this circuit in the lab →
What you need
- 2× NOR (inputs tied): A1' = NOR(A1, A1) and A0' = NOR(A0, A0)
- 4× NOR: Y0 = NOR(A1, A0), Y1 = NOR(A1, A0'), Y2 = NOR(A1', A0), Y3 = NOR(A1', A0')
Step by step
- Place inputs
A1andA0and probesY0toY3. - Make the complements: a NOR with both inputs on A1 gives A1', and one on A0 gives A0'.
- Y0: NOR A1 with A0. Y1: NOR A1 with A0'. Y2: NOR A1' with A0. Y3: NOR A1' with A0'.
- Count A1 A0 through 00, 01, 10, 11: the lit output moves from Y0 to Y3.
2-to-4 decoder truth table
| A1 | A0 | Y0 | Y1 | Y2 | Y3 |
|---|---|---|---|---|---|
| 0 | 0 | 1 | 0 | 0 | 0 |
| 0 | 1 | 0 | 1 | 0 | 0 |
| 1 | 0 | 0 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 1 |
All four rows of all four outputs are checked on the live circuit before the page is built.
You can also read the full theory in the lesson on the decoder. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.
More builds: Universal gates: NAND only, NOR only
All 246 build guides, by topic
Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.
Open the 2-to-4 decoder from NOR gates in the lab →Frequently asked
How do you design a 2 to 4 decoder using NOR gates?
Make A1' and A0' with two NOR gates whose inputs are tied, then build each output as a NOR of the opposite literals: Y0 = NOR(A1, A0), Y1 = NOR(A1, A0'), Y2 = NOR(A1', A0), Y3 = NOR(A1', A0').
How many NOR gates are needed for a 2 to 4 decoder?
Six: two as inverters and four for the outputs. If the complemented inputs are already available, four NOR gates are enough.
Why does a NOR gate work as an AND in a decoder?
By De Morgan's law, NOR(x, y) = (x + y)' = x' y', an AND of the complements. Feeding it the opposite of each literal you want gives the AND you need.
How do you add an enable to a NOR gate decoder?
Use an active-low enable E' as a third input on every output NOR gate. When E' = 1, every NOR outputs 0; when E' = 0, the decoder works normally.
What is the difference between a NAND and a NOR 2 to 4 decoder?
The NOR decoder has active-high outputs: the selected output is 1. The NAND decoder has active-low outputs: the selected output is 0 and the rest are 1, as in chips like the 74HC139.