Multiplexer using NAND gates: a 2-to-1 mux from 4 NANDs, live
A 2-to-1 multiplexer can be built from four NAND gates: one inverts the select line S, two gate the inputs (A with S' and B with S), and the fourth combines them, so Y = A when S = 0 and Y = B when S = 1.
The usual multiplexer is two AND gates, an OR gate and a NOT: Y = AS' + BS. That is a two-level AND-OR circuit, and any two-level AND-OR circuit keeps its function when every gate is replaced with a NAND, because NAND(NAND(x, y), NAND(z, w)) = xy + zw by De Morgan's law. The NOT becomes a NAND with both inputs tied to S. Compare the gate-level 2-to-1 multiplexer and the other gates built from NAND; the same trick turns any sum of products into NAND-NAND form, as the SOP vs POS circuit shows.
Open this circuit in the lab →
What you need
- 1× NAND: both inputs tied to S: S' = NOT S
- 2× NAND: N1 = NAND(A, S') and N2 = NAND(B, S)
- 1× NAND: Y = NAND(N1, N2) = AS' + BS
Step by step
- Place inputs
A,Band the selectS. - Feed S into both inputs of a NAND to make
S'. - NAND A with S' to get N1, and B with S to get N2. Only the input that S selects can pull its NAND low.
- NAND N1 and N2 together and probe the result as
Y. - Sweep all eight rows: with S = 0, Y follows A; with S = 1, Y follows B.
2-to-1 multiplexer truth table, NAND by NAND
| A | B | S | S' | N1 = NAND(A, S') | N2 = NAND(B, S) | Y |
|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 1 | 1 | 1 | 0 |
| 0 | 1 | 0 | 1 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 1 | 0 | 1 | 1 |
| 0 | 0 | 1 | 0 | 1 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 | 0 | 1 |
| 1 | 0 | 1 | 0 | 1 | 1 | 0 |
| 1 | 1 | 1 | 0 | 1 | 0 | 1 |
All eight rows are run through the circuit before the page is built and compared with Y = S ? B : A.
You can also read the full theory in the lesson on the multiplexer. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.
More builds: Universal gates: NAND only, NOR only
All 246 build guides, by topic
Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.
Open the 2-to-1 multiplexer from NAND gates in the lab →Frequently asked
How many NAND gates are needed for a 2-to-1 multiplexer?
Four. One NAND with both inputs tied to S makes S', two NANDs gate A with S' and B with S, and a fourth NAND combines them: Y = NAND(NAND(A, S'), NAND(B, S)) = AS' + BS.
How do you build a multiplexer using NAND gates?
Start from the AND-OR form Y = AS' + BS and replace every gate with a NAND. A two-level AND-OR circuit and the same circuit built from NANDs compute the same function by De Morgan's law, and the inverter for S is a NAND with its inputs tied together.
How do you build a 4-to-1 multiplexer using NAND gates?
Use three of these 2-to-1 multiplexers: two pick between I0 and I1 and between I2 and I3 using S0, and a third picks between their outputs using S1. That is 12 NAND gates; a two-level NAND-NAND design with shared inverters is another option.
Why is the multiplexer a universal element?
Because a 2-to-1 multiplexer alone can build any logic function: with constant inputs it becomes NOT, AND or OR. NAND is universal in the same way, which is why a multiplexer can be built from NANDs and NANDs can be built from multiplexers.