Logic gates using a 2:1 mux: NOT, AND, OR, NAND, NOR, XOR, live

Every basic logic gate can be made from one 2-to-1 multiplexer: put A on the select line and wire each data input to 0, 1, B or NOT B. AND is D0 = 0, D1 = B; OR is D0 = B, D1 = 1; NOT is D0 = 1, D1 = 0; XOR is D0 = B, D1 = NOT B. The live circuit below builds all seven gates from eight muxes and nothing else.

A 2-to-1 mux outputs D0 when its select S is 0 and D1 when S is 1, so with A on the select, D0 is what the gate must output when A = 0 and D1 is what it must output when A = 1. Each of those is a function of B alone, and a function of one variable can only be 0, 1, B or NOT B. Read the two halves of a gate's truth table and the wiring follows: AND gives 0 when A = 0 and B when A = 1, so D0 = 0 and D1 = B. OR gives B when A = 0 and 1 when A = 1. NAND and NOR are the same with the B half inverted, and XOR passes B or NOT B. NOT B itself is one more mux, with B on the select, 1 on D0 and 0 on D1, so the whole circuit uses only multiplexers and the constants 0 and 1. That is why the 2-to-1 mux is called a universal logic element, like the NAND gate and the NOR gate, as long as constant 0 and 1 are available. Each MUX block here is the 2-to-1 multiplexer from logic gates, saved as a part; open the circuit in the lab to look inside. The same method builds bigger circuits: the half adder using 2:1 muxes and the full adder using 4:1 muxes.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

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<iframe src="https://digiwleea.wleeaf.dev/embed/?c=H4sIAAAAAAAAA-2bS28bNxDHv0rBswws37u6pSgK9FAH6ANIEPggS6qxqL0y9IgdBP7uhaR9zGj-1NJ2k0Pgm73eH3c4HP45HNJf1T-r9d1sq6ZqUd_UD7fL5exiXq_nu3qrJurzcr2pV42a6olqZndLNVW3q5t6fnEz2y43F7tN3dxc3O0e1UQ1y8ftbws11YWeqLrZbGfNfLlR009fVb1QUzXXaqL-rZv9z3Vzv9s3v1rXN3Wjpl_V4-ETX9TUuaeJWq-2s-3hu8VE3c6ul7dqqt7t7Znd7pZqWjxNulZNXqtVqtWfYat2aPXzfH7apjm0qU8sHWg30DfNAtNGp2g_0He7RyM61PJFig9ZfPLzccDv16vrpTC_RPzg0Mv3f6mhtTLLGO9T1lR51sQiGTWXvxBzdJFljw0pe7TOM-i0hcGg939Qe8x5e9rW0sGi7Yg9rg2XpD2XJx5yWRalHeTzDNJnAoh5aCScW3tc2kNjAd0a5JIe-sANGgnp1iCf9tBYTLcGhaSHPhxcdDVRD_WaSuyD2Yf3rG3GH-3Yz4zrLryL7llvzoPRhBleEJBlkJGQZZABkCWQPUZBIEz7qKSIk0hJkAgQT5CYQoyhSBCIMbIznInCssMsPelMRZFSdqYiSAmQiiBlCjGBILYQiAmgM4zRIm6cJ0zVPSIIjYAqhWhNESsQraVlnHE5o2kpIcffgsCkRMhxcqREFESU32AEHXtTCMQAhI59_3eB0KB0hURoIHfLCUV0zjgGOvRODn3wsvucsTk-9rT_zgnEAy9zxueJWaAx5oKEAghMDkU5oAwyCCrl-CAoshFCcQBGlUGeRUKZhqh5PisWHFUOD2QAqA1nbOaKQ2XdO7DilGBiMyhrLXDMcXItcGAt4AyIBQYZBIFYQJCl8e1BLNgoh5VBocgZVusoIiPBOmAbYwywDUE05IIFkAYdYtBIVmCCTAsCDYXhBQEZujKEICFjgaAyCEQDW4GNlytwYNHg0xAb2ApAIBoYFGk02CChbsfAoCxl0AyRyqAjGCTGWDBICKKuiw5AQXqBQz7P3zSEYpBMKb_DEJkooJSPrpSxlIiXs4gzQBYgRAWoBMmCBksEh7SMHgY59KWsXNHTKV7KXNEDWeAMDQSw-2n7yHY_pZdOQJCjM7wMQLqBLHAo5kWcoxOiBLLgwAznUCXHyIEZzqAqa5HwtEeVFAXPvGABwxYJm4QCnayVlVAAM5xDLs_fns7XCsiCB3OcQyB_hNtuOieqCCA2-xyAWDi4JBQYVEkogHnOIF2AZSKAib6nriZqU980s9tjLaItFJ_Wa9vHrOB6NVHz1d39qlk2Wwa3lZWu4vH73x9-MtN9vG1Wu_V8ubfhuYXrtsmuTm1eWqY-RoX9FmXq05LyM8rUZ1qNqUb_hI2SAmCzkk0e20xWt0j5bwZq377fk47VrgHdflvbjNr1an1KW1JygHQ5UpfzdmSQPsKiXCVWJbZt0SJp0HTq6VaLwUJBES2R8nw2o42wi6UMnbNpnqHt2b5E-RFZvgHlO1rx0mDLVgGzGEMF2No-QPtanG8fEYSV73wK0XTt0qVkNF27ughjUCVHhqW0FuTOrI7rohycLhT9a8R3eMyE4Oppou7r5v16sVyr6adDU3tu_9JHdTVRu_vFbLtcvNseBGa-Xva_kSaP0kEPhV6j3btmW29vlwt6zhhfpt-uj8KXyTeUBmvOt_qrgqINzhZ1eV4hiTrf3602Ag_Z8tykcZ3kw9mjzc7405NRoIrxvMa1j-iULcFEMhJh2zww-QxgjEvK7zFcmAI5oEB6hAnto4T-Dm0Khn9HllGBaVVKgTsXsdUkdM8SIjy8IKCkCPd_JzpnOiRDsfYatPlyd7267aUkS3WOSQM9-_1BVOdMo69IGl-tZTRXRAmbyVcjmWoaTAMxkQc4ldx-0WAFmy9AlCn1KXoPnZSFy4T2gDoOzK-Y9Og0VCS1p39BnqsVKfUxsj9G9odpj5WIlW5m4mOlnwdNwNKjQVUK9ibI3jAX9D18zV6VatIx2PMyIS5Kl99AlUz1pkpYlVCGVZ3PsPxIhuXOa1o4j0NR0yXexMIUrYT-hdvYM7xJ9r86m-IZctljRJW5mkW5j7Uj-9gotmV9Kyklk5s_9BUrv8Ir37Z7ltAyowHU13BSidTxBVNIiF0t4WrWvlBKiF2u0fKkYSwzLKXSVkBoY3I3279AoHJkN4tWwkKuhOhWEoIMg8CtJOOldRwCp9HoS4wBh9FepscMASk1QNjlnyAje_SAht1LGl4QUPJikpHB86zUPWf1bJ6xfB4KeeTy5FtC_70SellCfcvn3_L5HzOfP8R6ZmFzrfhl5f9ZkfZOfFOk3GR-pFw6lsyPlEtHknkdoHvyc_kwkouP5PLtae5Lc_nWec_P5bPqtehMChZsk9l8t1MrJMQTZjsCmdg9S-XzMQ2ZpJpVMjVvn9m0mkWQz8eRfH54YeRL8u7QWBUaJPRgE8Az5kIyPM0OANIv2ASAfB5CcSyfj9I6DrGE3gHo-MzaVEo_vCAvPNpkUm-SEHdelBDzeCcEPpnVWxDg_f9gEKiS0OhlOgsuGyOIBh77l4PvsucYW-Kvnv4DW5rxrw05AAA" width="100%" height="420" style="border:0;border-radius:12px;max-width:640px" title="logic gates using 2:1 multiplexers circuit (digiwleea)" loading="lazy"></iframe>

To cite it: digiwleea, “logic gates using 2:1 multiplexers”, https://digiwleea.wleeaf.dev/tools/build/logic-gates-using-mux/

What you need

7× 2-to-1 MUX: one per gate, with S = A: NOT, AND, OR, NAND, NOR, XOR, XNOR
1× 2-to-1 MUX: NOT B, with S = B, D0 = 1, D1 = 0, shared by NAND, NOR, XOR and XNOR
2× constant: 0 (GND) and 1 (VDD) on the data inputs

Step by step

Place inputs A and B, a constant 0 and a constant 1, and one probe per gate.
Make NOT B: a mux with B on S, 1 on D0 and 0 on D1.
For each gate, place a mux with A on S and wire D0 and D1 from the table below.
Toggle A and B through 00, 01, 10 and 11: every probe follows its gate's truth table.

2:1 mux wiring for each gate (S = A)

Gate	D0 (A = 0)	D1 (A = 1)	Output
NOT A	1	0	A'
AND	0	B	AB
OR	B	1	A + B
NAND	1	NOT B	(AB)'
NOR	NOT B	0	(A + B)'
XOR	B	NOT B	A XOR B
XNOR	NOT B	B	A XNOR B

Truth table of the live circuit

A	B	NOT	AND	OR	NAND	NOR	XOR	XNOR
0	0	1	0	0	1	1	0	1
0	1	1	0	1	1	0	1	0
1	0	0	0	1	1	0	1	0
1	1	0	1	1	0	0	0	1

All four rows of all seven outputs are checked on the live circuit before the page is built. NOT here is NOT A; NOT B is the extra mux that feeds the inverted gates. A mux with its output fed back to one input also stores a bit: D latch and D flip-flop using a 2:1 mux.

You can also read the full theory in the lesson on the multiplexer as a universal block. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

More builds: Universal gates: NAND only, NOR only

XOR and XNOR from AND, OR and NOT gates 2-to-4 decoder from NOR gates NOT, OR, AND and XOR from NOR Toffoli gate NOT, AND, OR and NOR from NAND CNOT gate 2-to-1 multiplexer from NAND gates XOR gate from NAND gates SOP vs POS circuits XNOR gate from NAND gates full subtractor from NOR gates NOT gate from a NAND gate

All 246 build guides, by topic

Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the logic gates using 2:1 multiplexers in the lab →

Frequently asked

How do you implement an AND gate using a 2:1 mux?

Put A on the select line, connect D0 to 0 and D1 to B. When A = 0 the output is 0, and when A = 1 it is B, which is A AND B.

How do you implement an OR gate using a 2:1 mux?

Put A on the select line, connect D0 to B and D1 to 1. When A = 0 the output is B, and when A = 1 it is 1, which is A OR B.

How do you implement a NOT gate using a 2:1 mux?

Put A on the select line, connect D0 to 1 and D1 to 0. The output is 1 when A = 0 and 0 when A = 1.

How do you implement an XOR gate using a 2:1 mux?

Put A on the select line, connect D0 to B and D1 to NOT B. With only muxes, NOT B comes from a second mux with B on its select, 1 on D0 and 0 on D1, so XOR takes two 2:1 muxes.

How many 2:1 muxes are needed for a NAND gate?

Two: one makes NOT B, and the second, with A on the select, passes 1 when A = 0 and NOT B when A = 1. With a NOT gate available it is one mux.

Why is a 2:1 multiplexer a universal logic element?

Because it can make NOT and AND (or NAND) using only the constants 0 and 1, and every logic function can be built from those. In general any function of n variables fits a 2^n-to-1 mux, or a 2^(n-1)-to-1 mux with the last variable or its complement on the data inputs.