D latch and D flip-flop using a 2:1 mux, live
A D latch is a 2-to-1 multiplexer with its output fed back: EN drives the select, D goes to input 1 and the output Q goes back to input 0, so EN = 1 passes D and EN = 0 keeps Q. Two such latches in a row, opened on opposite clock levels, make a D flip-flop that captures D on the rising clock edge.
The mux does exactly what a latch needs: with the select at 1 it is transparent and copies D, and with the select at 0 it selects its own output, so whatever was there stays there. For the flip-flop, the master mux selects D while CLK = 0 and holds while CLK = 1, and the slave mux holds while CLK = 0 and copies the master while CLK = 1. When the clock rises the master freezes the last D and the slave starts showing it, so Q changes only at the rising edge; no inverter is needed because the two muxes simply use opposite inputs for D and feedback. One detail matters in real logic: a 2-to-1 mux built from gates, Y = A S' + B S, has a static-1 hazard. When the select changes while both inputs are 1, the AND that was on turns off a moment before the other turns on, the output can dip to 0, and a latch made from it then stores the dip. This simulator catches it too: the latch built from the plain 2-to-1 multiplexer lost its stored 1 when EN fell. The cure is the consensus term from hazard analysis, Y = A S' + B S + A B, which stays 1 through the change, so every MUX block here is that hazard-free mux, checked on all 8 rows; open the circuit in the lab to look inside. Chips usually build the same latch from transmission gates instead, as in the transmission-gate mux. The gate-level versions are the D latch and the master-slave D flip-flop.
Open this circuit in the lab →
What you need
- 1× 2-to-1 MUX: the D latch: S = EN, input 1 = D, input 0 = its own output QL
- 2× 2-to-1 MUX: the D flip-flop: a master (S = CLK, input 0 = D) and a slave (S = CLK, input 1 = master)
- 3× hazard-free MUX inside: each mux is Y = A S' + B S + A B (NOT, three AND, two OR)
Step by step
- Place inputs
DandEN, a clockCLK, and probesQL(latch) andQ(flip-flop). - D latch: a mux with EN on its select, D on input 1, and its own output wired back to input 0. Its output is QL.
- Master: a mux with CLK on its select, D on input 0 and its own output on input 1, so it follows D while CLK = 0.
- Slave: a mux with CLK on its select, the master on input 1 and its own output on input 0. Its output is Q.
- Turn EN off and change D: QL holds. Watch Q: it takes the value of D each time the clock rises.
What each output does
| Circuit | Mux select | Select = 0 | Select = 1 | Result |
|---|---|---|---|---|
| D latch | EN | Q (hold) | D (transparent) | QL = D while EN = 1, holds while EN = 0 |
| Master | CLK | D (follow) | its output (hold) | holds the D present at the rising edge |
| Slave | CLK | its output (hold) | master (copy) | Q = D sampled at each rising edge |
Before the page is built, the hazard-free mux is checked on all 8 rows and the circuit is run for 12 clocks with EN switching between transparent and hold; QL and Q are checked at every clock. D never changes in the same instant that EN falls, since a real latch needs D to stay steady for a short hold time around that moment.
You can also read the full theory in the lesson on the D latch. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.
More builds: Memory: latches and flip-flops
All 246 build guides, by topic
Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.
Open the D latch and D flip-flop using 2:1 muxes in the lab →Frequently asked
How do you make a D latch using a 2:1 mux?
Connect EN to the select line, D to input 1 and the output back to input 0. With EN = 1 the mux passes D, and with EN = 0 it passes its own output, so the value is held.
How do you make a D flip-flop using 2:1 muxes?
Use two mux latches in a master-slave pair on the same clock. The master selects D while CLK = 0 and holds while CLK = 1; the slave holds while CLK = 0 and copies the master while CLK = 1. Q then changes only on the rising edge.
How many 2:1 muxes are needed for a D flip-flop?
Two, one for the master latch and one for the slave latch. A D latch needs only one.
Why can a mux-based latch fail?
A gate-level mux, Y = A S' + B S, can glitch to 0 for a moment when the select changes while both inputs are 1, and the latch then stores the glitch. Adding the consensus term A B makes the mux hazard-free.
What is the difference between a D latch and a D flip-flop?
A D latch is level-sensitive: its output follows D for as long as EN is 1. A D flip-flop is edge-triggered: it takes D only at the clock edge and ignores D the rest of the time.