D latch using NAND gates: four gates, live

A gated D latch can be built from four NAND gates: S' = NAND(D, EN), R' = NAND(S', EN), and a cross-coupled NAND pair that holds the bit. While EN = 1, Q follows D; while EN = 0, Q holds.

The two NANDs on the right form an SR latch from NAND gates, which takes active-low inputs: a 0 on S' sets Q and a 0 on R' resets it, and 1 on both holds. The two NANDs on the left drive it. With EN = 0 both of their outputs are 1, so the latch holds. With EN = 1, S' = NOT D and R' = NAND(NOT D, 1) = D, so D = 1 pulls S' low and sets Q, and D = 0 pulls R' low and resets it. Feeding S' into the second gate instead of a separate NOT D saves the inverter, and S' and R' can never both be 0, so the SR latch's forbidden input never happens. The NOR version is the gated D latch using NOR gates; two of these latches, enabled on opposite clock levels, make the edge-triggered D flip-flop using NAND gates.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

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To cite it: digiwleea, “D latch from NAND gates”, https://digiwleea.wleeaf.dev/tools/build/d-latch-nand/

What you need

1× NAND: S' = NAND(D, EN)
1× NAND: R' = NAND(S', EN), which is D while EN = 1
2× NAND: cross-coupled: Q = NAND(S', Qbar) and Qbar = NAND(R', Q)

Step by step

Place inputs D and EN and probes Q and Qbar.
Cross-couple two NAND gates: each one's output feeds one input of the other. Their free inputs are S' and R'.
S' = NAND(D, EN) into the gate that drives Q.
R' = NAND(S', EN) into the gate that drives Qbar.
With EN = 1, toggle D: Q follows. Set EN = 0 and toggle D: Q holds.

D latch from NAND gates: truth table

EN	D	S'	R'	Q (next)
0	x	1	1	hold
1	0	1	0	0
1	1	0	1	1

The live circuit is stepped through follow, hold and follow again (8 steps, with the latch state carried from step to step) before the page is built.

You can also read the full theory in the lesson on the gated D latch. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

More builds: Memory: latches and flip-flops

D latch D flip-flop SR flip-flop from NOR gates D latch vs D flip-flop SR flip-flop from NAND gates D flip-flop from NAND gates SR latch from NAND gates D flip-flop from NOR gates SR latch D latch and D flip-flop using 2:1 muxes switch debouncer (SR latch)D flip-flop with enable

All 246 build guides, by topic

Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the D latch from NAND gates in the lab →

Frequently asked

How do you make a D latch using NAND gates?

Use four NANDs: S' = NAND(D, EN), R' = NAND(S', EN), and two cross-coupled NANDs for the latch. With EN = 1 the output follows D; with EN = 0 it holds.

How many NAND gates does a D latch need?

Four, if the second input gate takes S' instead of NOT D. The common textbook version uses four NANDs plus an inverter for NOT D, five gates in all.

What is the difference between a NAND and a NOR D latch?

They behave the same from outside. Inside, the NAND latch is set and reset by 0s (active-low) and the NOR latch by 1s, so the gating logic in front differs.