D flip-flop using NOR gates: master-slave, live

A positive-edge D flip-flop can be built from ten NOR gates: two NOR-only gated D latches as master and slave, plus one NOR to invert D and one to invert the clock. Q takes the value of D only at the rising edge of the clock.

With NOR gates the latch is set and reset by 1s, so its gating has to produce S = D AND EN and R = NOT D AND EN, and with NOR that means NORing the complements: S = NOR(NOT D, NOT EN) and R = NOR(D, NOT EN). For the master the enable is NOT CLK, so NOT EN is simply CLK and no inverter is needed there: the master is transparent while CLK is 0. The slave is enabled by CLK, so its NOT EN is a NOR inverter on the clock, and it copies the master: S = NOR(master Qbar, NOT CLK), R = NOR(master Q, NOT CLK). The two latches are never open at once, so D passes to Q only when the clock rises. The NAND version is the D flip-flop using NAND gates (nine gates), and a single NOR latch is the gated D latch; the D latch vs flip-flop page shows the difference in one circuit.

Open this circuit in the lab →

What you need

• 1× NOR: NOT D, inputs tied
• 2× NOR: master gating: S = NOR(NOT D, CLK), R = NOR(D, CLK)
• 2× NOR: master SR latch, cross-coupled
• 1× NOR: NOT CLK, inputs tied
• 2× NOR: slave gating: S = NOR(master Qbar, NOT CLK), R = NOR(master Q, NOT CLK)
• 2× NOR: slave SR latch, giving Q and Qbar

Step by step

1. Place a clock CLK and an input D, and probes Q and Qbar.
2. Invert D with a NOR whose inputs are tied, then build the master's gating: S = NOR(NOT D, CLK) and R = NOR(D, CLK).
3. Cross-couple two NORs as the master latch: R drives the gate whose output is the master's Q, S the gate whose output is its Qbar.
4. Invert CLK with another NOR, and build the slave the same way with the master's outputs as its data and NOT CLK in the gating.
5. Set D and give the clock a rising edge: Q copies D. Change D while the clock is high or low and Q holds until the next rising edge.

D flip-flop truth table

Before the page is built the circuit is stepped through 12 clock and data changes with its memory carried from step to step, including D changing while the clock is high and while it is low; Q and Qbar change only on rising edges. The level-triggered version, a single gated latch, is the gated D latch using NOR gates.

You can also read the full theory in the lesson on the D flip-flop. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

More builds: Memory: latches and flip-flops

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Frequently asked

How many NOR gates are needed for a D flip-flop?

Ten in this master-slave design: two cross-coupled NORs and two gating NORs for each latch, plus one NOR to invert D and one to invert the clock.

Why does a NOR D latch need the inverted inputs?

A NOR latch is set and reset by 1s, so it needs S = D AND EN and R = NOT D AND EN. A NOR gate gives an AND only of inverted signals: NOR(NOT D, NOT EN) = D AND EN.

How do you make a D flip-flop using NOR gates?

Build two gated D latches from NOR gates and chain them as master and slave on opposite clock levels. Each latch is a cross-coupled NOR pair set by NOR(NOT D, NOT EN) and reset by NOR(D, NOT EN); two more NORs with tied inputs make NOT D and NOT CLK. Ten NOR gates in all, and Q changes only on the rising clock edge.

What is the difference between a D latch and a D flip-flop made from NOR gates?

The single NOR D latch (often drawn as the clocked D flip-flop in textbooks) is level-triggered: Q follows D for as long as the clock or enable is 1. The master-slave version here adds a second latch, so Q changes only at the clock edge. The latch alone is the gated D latch using NOR gates.

Is a NOR D flip-flop rising or falling edge triggered?

This one is rising-edge: the master is open while the clock is 0 and the slave while it is 1, so the value reaches Q when the clock goes from 0 to 1. Swapping the two enables makes it falling-edge.