JK flip-flop using NOR gates: master-slave circuit, live
A JK flip-flop can be built from NOR gates: two NOR gates gate J and K with the clock and the fed-back output, and two cross-coupled NOR gates hold the bit. This live one is the master-slave version, eight NOR-based gates in two latches, so Q changes once on each falling clock edge: J = 1 sets, K = 1 resets, both 0 hold and both 1 toggle.
NOR is the dual of NAND, so the NOR circuit mirrors the master-slave JK flip-flop from NAND gates. A NOR latch is set and reset by active-high inputs, so its input gates must produce J AND CLK AND NOT Q and K AND CLK AND Q. A NOR gate computes an AND of inverted inputs, so the set gate is NOR(NOT J, NOT CLK, Q) and the reset gate is NOR(NOT K, NOT CLK, NOT Q); three inverters make NOT J, NOT K and NOT CLK. These two gates drive the master NOR SR latch. Feeding Q back is what makes J = K = 1 toggle, and it is also why a single clocked JK latch has the race-around condition: with the clock held high it would keep toggling. So a slave latch follows: two more NOR gates, NOR(NOT M, CLK) and NOR(M, CLK), pass the master's state only while CLK = 0, into a second NOR latch that drives Q and Qbar. The master listens while the clock is high, the slave copies it when the clock falls, and Q changes once per clock. Each 3-input NOR is drawn as an OR feeding a 2-input NOR, and an active-high CLR clears both latches to start Q at 0.
Open this circuit in the lab →
What you need
- 2× NOR (3-input): master input gates: NOR(J', CLK', Q) = J CLK Q' and NOR(K', CLK', Q') = K CLK Q
- 2× NOR: the master latch, cross-coupled (one also takes CLR through an OR)
- 2× NOR: slave input gates, open while CLK = 0 (the set gate also takes CLR)
- 2× NOR: the slave latch, giving Q and Qbar (Q's gate also takes CLR through an OR)
- 3× NOT: J', K' and CLK'
Step by step
- Place a clock
CLK, inputsJ,KandCLR, and probesQandQbar. - Invert J, K and CLK. Master input gates: NOR J', CLK' and Q (set), and NOR K', CLK' and Qbar (reset).
- Master latch: two cross-coupled NORs, the reset gate into M and the set gate into M'.
- Slave: NOR(M', CLK) and NOR(M, CLK) open only while the clock is 0, into a second cross-coupled NOR pair that drives Q and Qbar.
- Turn CLR off, then set J and K and watch Q change each time the clock falls: set, reset, hold and toggle.
JK truth table (on the falling clock edge)
| J | K | Q next | Action |
|---|---|---|---|
| 0 | 0 | Q | hold |
| 0 | 1 | 0 | reset |
| 1 | 0 | 1 | set |
| 1 | 1 | NOT Q | toggle |
Before the page is built, Q and Qbar are checked at every one of 13 clocks: a clear held for two clocks with J = 1 during the first, then hold, set, hold, reset, hold, three toggles in a row (one change per clock, no race-around), hold and reset. The characteristic equation is Q next = J Q' + K' Q.
You can also read the full theory in the lesson on the JK flip-flop. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.
More builds: Memory: latches and flip-flops
All 246 build guides, by topic
Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.
Open the JK flip-flop from NOR gates in the lab →Frequently asked
How do you make a JK flip-flop using NOR gates?
Gate J and K with the clock and the output: the set gate is NOR(NOT J, NOT CLK, Q) and the reset gate is NOR(NOT K, NOT CLK, NOT Q). They drive a cross-coupled NOR latch. For one change per clock, add a second NOR latch as a slave that copies the first when the clock falls.
What is the difference between a NAND and a NOR JK flip-flop?
They do the same job with dual gates. A NAND latch has active-low inputs, so its input gates are NANDs of J, CLK and Qbar; a NOR latch has active-high inputs, so its input gates are NORs of the inverted signals, which is the same AND written another way.
Why are Q and Qbar fed back in a JK flip-flop?
So that J = K = 1 toggles instead of being forbidden: the set gate is only enabled while Q = 0 and the reset gate only while Q = 1, so exactly one of them acts and the output flips.
How many NOR gates does a JK flip-flop need?
The simple clocked latch needs four: two 3-input NORs for the inputs and two for the latch, plus inverters for J, K and the clock, and it suffers race-around. The master-slave version needs eight NOR gates.
What is the race-around condition?
In a level-triggered JK latch with J = K = 1, the output toggles, the new output re-enables the opposite input, and it toggles again for as long as the clock is high. A master-slave or edge-triggered design limits it to one change per clock.