T flip-flop using NAND gates: master-slave circuit, live
A T flip-flop can be built from NAND gates by taking a JK flip-flop and joining J and K into one input T. With T = 0 it holds its bit; with T = 1 it toggles once per clock. This live one is the eight-NAND master-slave design, so Q changes once on each falling clock edge.
The textbook drawing of a T flip-flop from NAND gates is the four-NAND clocked JK latch with J and K tied together: two 3-input input gates, NAND(T, CLK, NOT Q) and NAND(T, CLK, Q), feeding a cross-coupled NAND pair. That circuit has a real flaw. With T = 1 and the clock held high, the output toggles, the new output re-enables the other input gate, and it toggles again, over and over, for as long as the clock is high: the race-around condition. So the working version adds a second latch. The master (the first four NANDs) follows T while CLK = 1, and the slave (four more NANDs, enabled by NOT CLK) copies the master when the clock falls, so Q can change only once per clock. This is the master-slave JK flip-flop from NAND gates with one input wire instead of two; each 3-input NAND is drawn as an AND feeding a 2-input NAND, and an active-high CLR starts Q at 0. The same flip-flop as a block is the T flip-flop from a JK flip-flop, and the edge-triggered version built on a D flip-flop is the T flip-flop using a D flip-flop.
Open this circuit in the lab →
What you need
- 2× NAND (3-input): master input gates: NAND(T, CLK, NOT Q) and NAND(T, CLK, Q), each an AND then a NAND
- 2× NAND: the master latch, cross-coupled (one also takes CLR through an AND)
- 2× NAND: slave input gates, enabled by NOT CLK
- 2× NAND: the slave latch, giving Q and Qbar
- 2× NOT: NOT CLK for the slave and NOT CLR for the clear
Step by step
- Place a clock
CLK, inputsTandCLR, and probesQandQbar. - Master input gates: NAND T with CLK and Qbar, and NAND T with CLK and Q. The feedback from Q and Qbar is what turns T = 1 into a toggle.
- Master latch: cross-couple two NANDs, one fed by each input gate.
- Slave: two NANDs pass the master's outputs only when NOT CLK is 1, into a second cross-coupled pair that drives Q and Qbar.
- Turn CLR off and set T = 1: Q flips on every falling clock edge, half the clock frequency. Set T = 0 and Q holds.
T flip-flop truth table (on the falling clock edge)
| T | Q | Q next | Action |
|---|---|---|---|
| 0 | 0 | 0 | hold |
| 0 | 1 | 1 | hold |
| 1 | 0 | 1 | toggle |
| 1 | 1 | 0 | toggle |
The characteristic equation is Q next = T XOR Q. Before the page is built, Q and Qbar are checked at every one of 13 clocks: a clear held for two clocks with T = 1 during the first (Q stays 0), single toggles, holds, and three toggles in a row with one change per clock, so no race-around.
You can also read the full theory in the lesson on the T flip-flop. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.
More builds: Memory: latches and flip-flops
All 246 build guides, by topic
Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.
Open the T flip-flop from NAND gates in the lab →Frequently asked
How do you make a T flip-flop using NAND gates?
Build a JK flip-flop from NAND gates and connect J and K together as T. To avoid the race-around condition, use the master-slave form: a NAND master latch that follows T while the clock is high and a NAND slave latch that copies it when the clock falls.
How many NAND gates does a T flip-flop need?
Four in the simple clocked latch (two 3-input and two 2-input NANDs), which suffers race-around with T = 1. The master-slave version needs eight NANDs plus an inverter for the clock.
Why does a NAND T flip-flop toggle more than once?
In the four-NAND latch, the output feeds back to the input gates, so while the clock stays high with T = 1 every toggle enables the next one. A master-slave design or an edge-triggered flip-flop limits it to one change per clock.
What is the characteristic equation of a T flip-flop?
Q next = T XOR Q, also written T Q' + T' Q. T = 0 keeps the bit and T = 1 inverts it.
Where are T flip-flops used?
In counters and frequency dividers. A T flip-flop with T = 1 divides its clock by two, and a chain of them makes a ripple counter.