JK flip-flop using a D flip-flop: D = JQ' + K'Q, live

To make a JK flip-flop from a D flip-flop, feed it D = JQ' + K'Q: J = 1 sets Q, K = 1 resets it, J = K = 0 holds, and J = K = 1 toggles. The live circuit below is a D flip-flop with one NOT, two ANDs and one OR.

This is the D to JK conversion, done by the usual method. A D flip-flop stores whatever is on D at the clock edge, so D must equal the JK flip-flop's next state. Write the JK characteristic table for every J, K and Q (eight rows), take the Q next column as D, and simplify with a K-map: the 1s group into JQ' (set from 0, or toggle from 0) and K'Q (keep a 1 unless K resets it). That is exactly the JK characteristic equation, which is why the conversion needs no excitation table lookup. Unlike the SR to D or JK to D conversions, Q must be fed back here: the hold and toggle rows depend on the current state. This circuit takes Q' from the flip-flop's QN output, so only K needs an inverter. The D flip-flop is the master-slave design with a clear (CLR) used across these pages, so Q changes on the rising clock edge, and because the D flip-flop samples only at the edge, J = K = 1 toggles exactly once per clock with no race-around problem.

Open this circuit in the lab →

What you need

• 1× D flip-flop: master-slave, with a clear (CLR)
• 1× NOT: K'
• 2× AND: J Q' (from QN) and K' Q
• 1× OR: D = JQ' + K'Q

Step by step

1. Place inputs J, K, CLK and CLR, a D flip-flop, and probes Q and QN.
2. AND J with QN: J Q'.
3. Invert K and AND it with Q: K' Q.
4. OR the two terms and wire the result to D: D = JQ' + K'Q.
5. Turn CLR on, clock once, and turn it off: Q starts at 0.
6. Set J = 1 and clock: Q becomes 1. J = K = 0 holds, K = 1 resets, and J = K = 1 toggles Q on every clock.

D to JK conversion table

D is the value Q takes at the next rising clock edge. Before the page is built, the live circuit runs 12 clocks through clear, set, hold, reset and three toggles in a row, and Q and QN are checked after every edge. The opposite direction (JK to D) runs live with the full flip-flop conversion table, and the SR version as SR flip-flop using a D flip-flop.

You can also read the full theory in the lesson on flip-flop types and excitation tables. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

More builds: Memory: latches and flip-flops

All 246 build guides, by topic

Frequently asked

How do you convert a D flip-flop to a JK flip-flop?

Feed the D input with D = JQ' + K'Q. That takes one inverter for K', two AND gates (J with Q', K' with Q) and one OR gate; Q' can come from the flip-flop's own Q-bar output.

Why does the D to JK conversion need feedback from Q?

A JK flip-flop's hold and toggle modes depend on the current state: with J = K = 0 the next state is Q, and with J = K = 1 it is Q'. A D flip-flop has no memory of its own input, so the logic in front of it must see Q to produce those values.

Does a JK flip-flop built from a D flip-flop have a race-around problem?

No, as long as the D flip-flop is edge-triggered. It samples D once per clock edge, so with J = K = 1 the output toggles exactly once per clock. Race-around happens in a level-triggered JK latch, where the output can toggle repeatedly while the clock is high.

What is the K-map result for the D to JK conversion?

Plotting D over J, K and Q gives 1s at JKQ = 001, 100, 101 and 110. They group into J Q' (100, 110) and K' Q (001, 101), so D = JQ' + K'Q, the JK characteristic equation.

How do you convert a JK flip-flop to a D flip-flop?

Connect J = D and K = NOT D. Then D = 1 sets and D = 0 resets on the clock edge, so Q follows D.