SR to D flip-flop conversion: S = D, R = NOT D, live
To convert an SR flip-flop into a D flip-flop, connect S = D and R = NOT D through one inverter. D = 1 sets the flip-flop and D = 0 resets it on the clock edge, and because S and R are always opposite, the forbidden S = R = 1 input can never occur.
This is the usual conversion recipe. The D flip-flop's characteristic table says Q next = D. From the SR excitation table, a next state of 1 needs S = 1, R = 0 (or a hold when Q is already 1), and a next state of 0 needs S = 0, R = 1; choosing S = D and R = D' satisfies every row whatever Q is, so no feedback from Q is needed. The inverter has a second job: an SR flip-flop with both inputs at 1 is undefined, and a D flip-flop simply cannot produce that input. The SR flip-flop here is the edge-triggered SR flip-flop from a D flip-flop, saved as a part, so Q changes on the rising clock edge, and CLR forces Q to 0 to start. The reverse direction is that same page (D = S + R'Q), and with a clocked SR latch instead of an edge-triggered flip-flop the same wiring gives the gated D latch. All the common pairings are in the flip-flop conversion table.
Open this circuit in the lab →
What you need
- 1× SR flip-flop: edge-triggered, with clear
- 1× NOT: R = NOT D
Step by step
- Place inputs
D,CLKandCLR, an SR flip-flop and probesQandQN. - Wire D straight to S.
- Invert D and wire it to R.
- Turn CLR on for a clock, then off: Q starts at 0.
- Set D and clock: Q copies D at each rising edge.
SR to D conversion table
| D | S = D | R = D' | Q next |
|---|---|---|---|
| 0 | 0 | 1 | 0 (reset) |
| 1 | 1 | 0 | 1 (set) |
S and R are never both 1. Before the page is built, the live circuit runs 12 clocks after a clear with D switching between 0 and 1, and Q and QN are checked after every edge.
You can also read the full theory in the lesson on flip-flop types and excitation tables. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.
More builds: Memory: latches and flip-flops
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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.
Open the D flip-flop from an SR flip-flop in the lab →Frequently asked
How do you convert an SR flip-flop to a D flip-flop?
Connect S = D and R = NOT D, using one inverter. D = 1 sets the flip-flop and D = 0 resets it, so Q follows D on every clock edge.
Why does the SR to D conversion remove the invalid state?
Because S and R come from D and its inverse, they are always opposite, so S = R = 1 can never be applied.
Does the SR to D conversion need feedback from Q?
No. S = D and R = D' already give the right next state in every case, so unlike the JK or T conversions, Q is not fed back.
How do you convert a D flip-flop to an SR flip-flop?
Feed D = S + R'Q: S sets, R resets, and with both at 0 the flip-flop reloads its own Q.