SR flip-flop using a D flip-flop: D = S + R'Q, live
To make an SR flip-flop from a D flip-flop, feed it D = S + R'Q: S = 1 sets Q, R = 1 resets it, and with both at 0 the flip-flop reloads its own Q and holds. The live circuit below is a D flip-flop with one NOT, one AND and one OR.
The method is the usual flip-flop conversion. The SR characteristic table says Q next is 1 after a set, 0 after a reset and Q when neither is active; a D flip-flop simply stores D, so D must equal that next state. A K-map over S, R and Q, with S = R = 1 as a don't-care, simplifies it to D = S + R'Q. The AND gate keeps Q while R is 0, the OR forces a 1 when S is 1. One consequence is worth knowing: S = R = 1 is forbidden for a true SR flip-flop, but this circuit gives it a defined meaning, set, because the S term wins the OR. The D flip-flop is the master-slave design with an asynchronous clear used across these pages, so Q changes on the rising clock edge and CLR forces Q to 0 to start. The same idea makes the JK flip-flop from a D flip-flop (D = J Q' + K' Q) and the T flip-flop from a D flip-flop (D = T XOR Q), and the flip-flop conversion page lists every pairing. For the gate-level SR flip-flop itself, see the clocked SR flip-flop from NAND gates. Gating S and R with Q turns this SR flip-flop into the JK flip-flop from an SR flip-flop.
Open this circuit in the lab →
What you need
- 1× D flip-flop: master-slave, with an asynchronous clear (CLR)
- 1× NOT: R'
- 1× AND: R'Q, which keeps the stored bit while R = 0
- 1× OR: D = S + R'Q
Step by step
- Place inputs
S,R,CLKandCLR, a D flip-flop, and probesQandQN. - Invert R and AND it with Q: R'Q.
- OR that with S and wire the result to D: D = S + R'Q.
- Turn CLR on, clock once, and turn it off: Q starts at 0.
- Set S = 1 and clock: Q becomes 1. Back to S = 0: Q holds. R = 1 and clock: Q becomes 0.
SR flip-flop from D: truth table
| S | R | D = S + R'Q | Q next | Mode |
|---|---|---|---|---|
| 0 | 0 | Q | Q | hold |
| 0 | 1 | 0 | 0 | reset |
| 1 | 0 | 1 | 1 | set |
| 1 | 1 | 1 | 1 | forbidden for SR; sets here |
Q next is the value after the rising clock edge. Before the page is built, the live circuit runs 12 clocks through clear, set, hold, reset and the S = R = 1 case, and Q and QN are checked after every edge. The opposite conversion, a D flip-flop built on this SR flip-flop, is SR to D flip-flop conversion. With one more AND gate the same idea makes a JK: JK flip-flop using a D flip-flop.
You can also read the full theory in the lesson on flip-flop types and excitation tables. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.
More builds: Memory: latches and flip-flops
All 246 build guides, by topic
Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.
Open the SR flip-flop from a D flip-flop in the lab →Frequently asked
How do you convert a D flip-flop to an SR flip-flop?
Feed the D input with D = S + R'Q. S = 1 makes D = 1 (set), R = 1 with S = 0 makes D = 0 (reset), and S = R = 0 makes D = Q, so the flip-flop holds.
What happens when S = R = 1 in this circuit?
D = S + R'Q is 1, so the flip-flop sets. A true SR flip-flop leaves S = R = 1 forbidden; this conversion treats it as a don't-care that the K-map turned into set.
What is the characteristic equation of an SR flip-flop?
Q next = S + R'Q, with the condition S R = 0. It is the same expression this circuit feeds to the D input.
How do you make a JK flip-flop from an SR flip-flop?
Gate the inputs with the output: S = J Q' and R = K Q. Then S and R are never both 1, and J = K = 1 toggles.