T flip-flop using a JK flip-flop: J = K = T, live
To make a T flip-flop from a JK flip-flop, tie J and K together and call the joined input T. With T = 0 the JK holds its bit, and with T = 1 it toggles on every clock edge, which is exactly a T flip-flop. The live circuit below runs it.
A JK flip-flop has four modes: J K = 00 holds, 10 sets, 01 resets and 11 toggles. Tying J to K leaves only the two modes where they are equal, hold and toggle, so the characteristic equation becomes Q+ = T XOR Q. The same answer falls out of the formal method: the T flip-flop's table says Q must change when T = 1, the JK excitation table says a change from 0 to 1 needs J = 1 and a change from 1 to 0 needs K = 1, and J = K = T satisfies both. The JK here is the master-slave JK from NAND gates, saved as a part, so Q changes on the falling clock edge, and the master-slave design avoids the race-around condition that a level-triggered JK would hit with T held at 1. CLR forces Q to 0 so the toggling starts from a known state. Other routes to the same flip-flop: the same circuit drawn gate by gate, the T flip-flop using NAND gates; the T flip-flop from a D flip-flop (D = T XOR Q) and the full list of flip-flop conversions.
Open this circuit in the lab →
What you need
- 1× JK flip-flop: the 8-NAND master-slave circuit, with its clear; J and K both wired to T
Step by step
- Write the T flip-flop's characteristic table: Q next = Q when T = 0 and NOT Q when T = 1.
- From the JK excitation table, 0 to 1 needs J = 1 and 1 to 0 needs K = 1; holding needs J = 0 (from 0) or K = 0 (from 1).
- J = T and K = T meet every row, so connect J and K together as T.
- Turn CLR on and off to start at Q = 0, set T = 1 and run the clock: Q flips on every falling edge, dividing the clock by two.
- Set T = 0: Q holds whatever it was.
T flip-flop from JK: truth table
| T | J | K | Q | Q next | Mode |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | hold |
| 0 | 0 | 0 | 1 | 1 | hold |
| 1 | 1 | 1 | 0 | 1 | toggle |
| 1 | 1 | 1 | 1 | 0 | toggle |
Q next is the value after the falling clock edge. Before the page is built, the live circuit is run for 12 clocks with T switching between hold and toggle, and Q and Qbar are checked after every edge. Add an XOR, T = D XOR Q, and this T flip-flop becomes a D flip-flop: D flip-flop using a T flip-flop.
You can also read the full theory in the lesson on the T flip-flop. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.
More builds: Memory: latches and flip-flops
All 246 build guides, by topic
Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.
Open the T flip-flop from a JK flip-flop in the lab →Frequently asked
How do you convert a JK flip-flop to a T flip-flop?
Connect J and K together and use the joined input as T. J = K = 0 holds and J = K = 1 toggles, which are the two modes of a T flip-flop.
What is the characteristic equation of a T flip-flop?
Q+ = T XOR Q, also written T Q' + T' Q. With T = 0 the next state equals Q, and with T = 1 it is NOT Q.
Why is a T flip-flop with T = 1 a divide-by-2 counter?
It toggles once per clock edge, so its output completes one full cycle for every two clock cycles: half the clock frequency. Chaining T flip-flops this way makes a ripple counter.
How do you make a T flip-flop from a D flip-flop?
Feed D = T XOR Q. The XOR passes Q through when T = 0 and inverts it when T = 1.