D flip-flop with enable: hold or load, live
A D flip-flop with enable loads D on a rising clock edge only while EN is 1; while EN is 0 it keeps its value however D changes. It is an ordinary D flip-flop with a 2-to-1 multiplexer in front of D that feeds Q back when EN is 0: D' = EN AND D, OR NOT EN AND Q.
Every register bit needs this: a register should hold its word until told to load, while the clock keeps running for everything else. The tempting shortcut, ANDing the clock with EN, is clock gating, and with a plain AND gate it can cut a clock pulse short or add an extra edge if EN changes while the clock is high, and it delays this flip-flop's clock relative to the others. The multiplexer leaves the clock alone: on every edge the flip-flop loads something, either the new D or its own Q again. The flip-flop here is the verified D flip-flop with clear, saved as a part, and CLR forces Q to 0. The live circuit opens with CLR on and CLK as a switch you click: switch CLR to 0, set D and EN to 1, then click CLK up and Q takes D on that rising edge. Four of these sharing one load signal make a 4-bit register with parallel load.
Open this circuit in the lab →
What you need
- 1× D flip-flop with clear: stores Q on the rising edge; CLR forces 0
- 1× NOT: NOT EN
- 2× AND: EN AND D, and NOT EN AND Q
- 1× OR: the mux output, into the flip-flop's D
Step by step
- Place inputs
D,EN,CLKandCLR, a D flip-flop with clear, and probesQandQN. - Build a 2-to-1 multiplexer from a NOT, two ANDs and an OR: EN AND D on one side, NOT EN AND Q on the other.
- Wire the multiplexer output to the flip-flop's D, the clock to CLK and CLR to its clear input.
- Feed the flip-flop's Q back into the multiplexer, and probe Q and QN.
- Switch CLR off. With EN = 0, set D and pulse CLK: Q stays put. Set EN = 1 and pulse CLK again: Q takes D on the rising edge.
D flip-flop with enable: characteristic table
| CLR | EN | D | Q after the rising edge |
|---|---|---|---|
| 1 | x | x | 0 |
| 0 | 0 | x | Q (hold) |
| 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 1 |
x means either value. The run checks Q and QN over 12 clock edges of clears, loads and holds before the page is built, including an edge where D is 1 but EN is 0 and Q stays 0. Compare the plain D flip-flop, which loads on every edge, and the D latch, whose enable makes it transparent instead of edge-triggered.
You can also read the full theory in the lesson on the register bit. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.
More builds: Memory: latches and flip-flops
All 246 build guides, by topic
Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.
Open the D flip-flop with enable in the lab →Frequently asked
What is a D flip-flop with enable?
A D flip-flop that loads its D input on a clock edge only when an enable input EN is 1. When EN is 0 it holds its stored value on every edge, whatever D does.
How do you add an enable to a D flip-flop?
Put a 2-to-1 multiplexer in front of D, selected by EN: one data input is the new value D and the other is the flip-flop's own output Q. With EN = 0 the flip-flop reloads Q on each edge, so it holds.
Why not just AND the clock with the enable?
That is clock gating. With a plain AND gate, EN changing while the clock is high can shorten a clock pulse or create an extra edge, and the gate delays this flip-flop's clock relative to the rest. Chips that gate clocks use dedicated clock-gating cells built around a latch; the multiplexer avoids the problem altogether.
What is the difference between a D latch enable and a D flip-flop enable?
A D latch's enable makes it transparent: Q follows D the whole time EN is 1. A D flip-flop with enable still changes only on the clock edge; EN only decides whether that edge loads D or keeps Q.