JK flip-flop using an SR flip-flop: S = JQ', R = KQ, live
To make a JK flip-flop from an SR flip-flop, gate the inputs with the output: S = J AND Q' and R = K AND Q. S and R can then never both be 1, and J = K = 1 makes the flip-flop toggle instead of hitting the SR flip-flop's forbidden input.
The conversion follows the usual recipe. The JK characteristic table says: J K = 00 holds, 10 sets, 01 resets, 11 toggles. From the SR excitation table, going from 0 to 1 needs S = 1, going from 1 to 0 needs R = 1, and holding needs the opposite input at 0. Filling in S and R for every J, K and Q and simplifying gives S = J Q' and R = K Q. The gating is what removes the forbidden case: S can only be 1 while Q = 0 and R only while Q = 1, so with J = K = 1 the flip-flop sets when it is 0 and resets when it is 1, which is a toggle. The SR flip-flop here is the edge-triggered SR flip-flop from a D flip-flop, saved as a part, so the toggle happens once per rising clock edge; built on a level-triggered SR latch instead, the same wiring would suffer the race-around condition. CLR forces Q to 0 to start. See also the JK flip-flop from a D flip-flop and the full table of flip-flop conversions.
Open this circuit in the lab →
What you need
- 1× SR flip-flop: edge-triggered, with clear (a D flip-flop with D = S + R'Q)
- 2× AND: S = J AND Q', R = K AND Q
Step by step
- Place inputs
J,K,CLKandCLR, an SR flip-flop and probesQandQN. - AND J with QN and wire it to S.
- AND K with Q and wire it to R.
- Turn CLR on, clock once, and turn it off: Q starts at 0.
- Try each mode with a clock: J = 1 sets, K = 1 resets, both 0 hold, both 1 toggle on every edge.
JK from SR: excitation table
| J | K | Q | S = JQ' | R = KQ | Q next |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 | 0 | 1 |
| 0 | 1 | 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 | 1 | 0 |
| 1 | 0 | 0 | 1 | 0 | 1 |
| 1 | 0 | 1 | 0 | 0 | 1 |
| 1 | 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 1 | 0 | 1 | 0 |
S and R are never 1 at the same time. Before the page is built, the live circuit runs 12 clocks through clear, set, hold, reset and three toggles in a row, and Q and QN are checked after every edge.
You can also read the full theory in the lesson on flip-flop types and excitation tables. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.
More builds: Memory: latches and flip-flops
All 246 build guides, by topic
Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.
Open the JK flip-flop from an SR flip-flop in the lab →Frequently asked
How do you convert an SR flip-flop to a JK flip-flop?
Connect S = J AND Q' and R = K AND Q. The SR flip-flop then holds, sets, resets and, with J = K = 1, toggles.
Why does the JK flip-flop not have a forbidden state?
Because its inputs are gated by Q: S can be 1 only while Q is 0 and R only while Q is 1, so the SR inputs are never both 1. J = K = 1 becomes a toggle.
How do you convert a JK flip-flop to an SR flip-flop?
Connect J = S and K = R and never drive both to 1. The JK then behaves as an SR flip-flop, and S = R = 1 would toggle rather than being forbidden.
What is the characteristic equation of a JK flip-flop?
Q next = J Q' + K' Q. It sets when J = 1 and Q = 0, keeps a 1 unless K = 1, and toggles when J = K = 1.