How to build a clocked SR flip-flop using NOR gates
A clocked SR flip-flop using NOR gates is a cross-coupled NOR latch whose S and R inputs only get through while CLK is 1. With NOR gates alone that takes seven: three NORs with tied inputs make S', R' and CLK', two NORs gate the inputs (NOR(S', CLK') = S AND CLK), and two cross-coupled NORs store the bit.
The cross-coupled pair on its own is the NOR SR latch, which is set and reset by 1s: a 1 on the gate that drives Q low resets it, a 1 on the other gate sets it. To add a clock, each input must reach the latch only when CLK is also 1, which is an AND. A NOR gives an AND only of inverted signals, NOR(S', CLK') = S AND CLK by De Morgan, so the all-NOR version first inverts S, R and CLK with three NORs whose inputs are tied together. Many textbooks draw the same circuit with two AND gates in front of the NOR latch; the behavior is identical and it uses four gates instead of seven. Compare the clocked SR flip-flop using NAND gates, which needs only four NANDs because each NAND gate already inverts, giving the active-low inputs the NAND latch wants. Strictly this is a level-triggered gated latch rather than an edge-triggered flip-flop, and S = R = 1 while CLK is 1 is still forbidden: it drives both outputs to 0, and when CLK falls the result depends on which gate is faster.
Open this circuit in the lab →
What you need
- 3× NOR: inverters with tied inputs: S', R' and CLK'
- 2× NOR: gating: NOR(S', CLK') = S CLK and NOR(R', CLK') = R CLK
- 2× NOR: the cross-coupled latch that stores Q and Qbar
Step by step
- Place inputs
S,RandCLK, and probesQandQbar. - Make S', R' and CLK' with three NOR gates, each with both inputs tied to one signal.
- Gate the inputs:
SG = NOR(S', CLK')andRG = NOR(R', CLK'). With CLK = 0 both are 0 no matter what S and R do. - Cross-couple two NORs:
Q = NOR(RG, Qbar)andQbar = NOR(SG, Q). - Set CLK = 1 and pulse S: Q goes to 1. Pulse R: Q goes to 0. Set CLK = 0 and change S and R: Q does not move.
Clocked SR flip-flop truth table (NOR)
| CLK | S | R | Q next | State |
|---|---|---|---|---|
| 0 | X | X | Q | hold (inputs ignored) |
| 1 | 0 | 0 | Q | hold |
| 1 | 0 | 1 | 0 | reset |
| 1 | 1 | 0 | 1 | set |
| 1 | 1 | 1 | 0 (Q = Qbar = 0) | invalid |
Before the page is built the circuit is stepped through 8 input changes with its memory carried between steps: set, hold, a reset attempt with CLK = 0 (ignored), reset, a set attempt with CLK = 0 (ignored), set, hold and reset. Q and Qbar matched at every step. The invalid row is listed for completeness and is not part of the run. Edge-triggered versions from NOR gates: the D flip-flop using NOR gates and the JK flip-flop using NOR gates.
You can also read the full theory in the lesson on the SR latch. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.
More builds: Memory: latches and flip-flops
All 246 build guides, by topic
Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.
Open the SR flip-flop from NOR gates in the lab →Frequently asked
How do you make an SR flip-flop using NOR gates?
Cross-couple two NOR gates as a latch, Q = NOR(RG, Qbar) and Qbar = NOR(SG, Q), and gate the inputs with the clock so that SG = S AND CLK and RG = R AND CLK. With NOR gates only, SG = NOR(S', CLK') and RG = NOR(R', CLK'), with three more NORs as inverters: seven in total.
How many NOR gates are needed for a clocked SR flip-flop?
Seven if only NOR gates are allowed: two for the latch, two for the clock gating and three inverters for S, R and CLK. With AND gates for the gating it is two ANDs and two NORs.
What happens when S = R = 1 in a NOR SR flip-flop?
While CLK is 1, both NOR outputs are forced to 0, so Q and Qbar are no longer complements. When CLK or the inputs return to 0 the latch settles into a state that depends on gate delays, which is why the input is forbidden.
What is the difference between the NOR and NAND SR flip-flop?
The NOR latch is set and reset by 1s and goes to Q = Qbar = 0 on the invalid input; the NAND latch is set and reset by 0s and goes to Q = Qbar = 1. With a clock, the NAND version needs four gates because its gating NANDs also invert the inputs; the all-NOR version needs seven.
Is a clocked SR flip-flop with NOR gates edge-triggered?
No. It is level-triggered: it follows S and R for as long as CLK is 1. For edge triggering, chain two of these latches as master and slave on opposite clock levels.