Sequence generator: a counter with decode logic, live
A sequence generator outputs a fixed pattern of bits, one per clock, over and over. This one generates 1, 0, 1, 1, 0, 0, 1, 0: a 3-bit counter steps through states 0 to 7, and a small decoder turns each state into that state's output bit, Z = Q2'Q0' + Q2'Q1 + Q1Q0'.
Counter plus decode is the most direct way to generate any repeating sequence: give each position in the sequence its own counter state, write a truth table from state to output, and minimize it. Here the counter is a 3-bit synchronous counter built from D flip-flops with a clear (Q0 toggles every clock, Q1 toggles when Q0 is 1, Q2 when Q1 and Q0 are both 1), and the output logic is the minimal sum of products of the pattern, which you can check with the Karnaugh map solver (minterms 0, 2, 3 and 6). A different pattern only changes the decoder. Another classic design feeds back a shift register (as in the ring counter or the LFSR), which can use fewer gates for some patterns; the counter design works for any pattern up to the counter's length. The live circuit opens with CLR on, because flip-flops start in an unknown state: turn CLR off and Z plays the sequence.
Open this circuit in the lab →
What you need
- 3× D flip-flop with clear: the counter, Q2 Q1 Q0
- 2× XOR: Q1 toggles with Q0; Q2 toggles with Q1 AND Q0
- 1× AND: Q1 AND Q0, for Q2's toggle
- 2× NOT: Q0' (also Q0's toggle) and Q2'
- 3× AND: the product terms Q2'Q0', Q2'Q1 and Q1Q0'
- 2× OR: Z, the sum of the three terms
Step by step
- Place a clock
CLK, an inputCLR, three D flip-flops with clear and probesQ2,Q1,Q0andZ. - Make a counter: D0 = NOT Q0, D1 = Q1 XOR Q0, D2 = Q2 XOR (Q1 AND Q0), all on one clock and one clear.
- Write the pattern's truth table, one row per state (below), and minimize it: Z = Q2'Q0' + Q2'Q1 + Q1Q0'.
- Build Z from three ANDs and two ORs. Turn CLR off and watch Z repeat 1, 0, 1, 1, 0, 0, 1, 0.
State and output
| State | Q2 Q1 Q0 | Z |
|---|---|---|
| 0 | 000 | 1 |
| 1 | 001 | 0 |
| 2 | 010 | 1 |
| 3 | 011 | 1 |
| 4 | 100 | 0 |
| 5 | 101 | 0 |
| 6 | 110 | 1 |
| 7 | 111 | 0 |
Before the page is built, a 22-clock run (a clear, the pattern twice and two more steps, then a clear in the middle and a restart) is checked on Q2, Q1, Q0 and Z after every clock.
You can also read the full theory in the lesson on counters. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.
More builds: State machines
All 246 build guides, by topic
Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.
Open the Sequence generator in the lab →Frequently asked
What is a sequence generator?
A sequential circuit that outputs a predefined sequence of bits, one per clock cycle, repeating it. It is used for test patterns, control timing and serial codes.
How do you design a sequence generator?
One way is a counter plus decode logic: use a counter with at least as many states as the sequence is long, write a truth table from each state to its output bit, and minimize it. Another is a shift register with feedback logic chosen so it shifts out the sequence.
How many flip-flops does a sequence generator need?
With the counter method, enough to count the sequence length: 3 flip-flops for up to 8 bits, 4 for up to 16. Shift-register designs need enough flip-flops that every position in the sequence has its own distinct state.
What is the difference between a sequence generator and a sequence detector?
A generator produces a pattern on its output; a detector watches an input stream and signals when a pattern appears, like the 1011 sequence detector.