Yosys and digiwleea: from Verilog to gates, two ways

Yosys, the Yosys Open SYnthesis Suite, is a free and open-source framework for RTL synthesis: it turns Verilog into a netlist of gates and cells. Its README describes extensive Verilog-2005 support, a synthesizable subset of SystemVerilog through the slang library, and a design where synthesis jobs are scripts that combine passes (algorithms), with more passes added in C++. It is licensed under the ISC license, is part of the free OSS CAD Suite and the commercial Tabby CAD Suite, and its latest release is v0.70 (October 13, 2026). Yosys turns hardware code into gates automatically; digiwleea has you build the gates by hand, so you know what Yosys is producing.

What Yosys is good at

Real synthesis, for free: read Verilog, optimize it, map it to a target's cells and write out a netlist for an FPGA or ASIC flow, all scriptable, with new passes addable in C++. It comes ready to use in the free OSS CAD Suite. (digiwleea is an independent project, not affiliated with YosysHQ.)

How digiwleea is different

digiwleea works in the opposite direction: you draw the circuit and the simulator shows how it behaves. In the browser you build NOT and NAND from CMOS transistors, then multiplexers, adders, flip-flops, counters, registers, RAM and an 8-bit CPU that runs a stored program, through a 40+ level course where every part is checked against its truth table, with an AI tutor (Wleea). It does not synthesize code; it exports circuits to Verilog and VHDL and imports a combinational subset of VHDL. Use it to learn what an always block, a mux or a register is made of, then read a Yosys netlist with that knowledge. The combinational Verilog and sequential Verilog lessons connect the two.

	Yosys	digiwleea
Direction	Code to gates (synthesis)	Gates you build, simulated live
Input	Verilog, a synthesizable subset of SystemVerilog	Circuits drawn from transistors up
Output	Netlists for FPGA and ASIC flows	Live wire values, truth tables, Verilog and VHDL export
Runs on	Command line (Linux, macOS, Windows builds)	Any modern browser
Price	Free, ISC license	Free lab and Act I; Premium for the full course

No sign-up is needed to start: open the lab and place your first transistor, or read the free theory course. The account (and the AI tutor) are optional.

More comparisons: HDL, FPGA and chip design tools

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See for yourself: build a logic gate from transistors in the simulator, then follow the path from sand to an 8-bit CPU.

Open the digiwleea lab →

Frequently asked

What is Yosys?

Yosys is a free, open-source framework for RTL synthesis. It reads Verilog (and a synthesizable subset of SystemVerilog) and produces a netlist of gates or FPGA cells, using scripts of synthesis passes.

Is Yosys free?

Yes. It is free software under the ISC license and is included in the free OSS CAD Suite. YosysHQ also sells the Tabby CAD Suite, which adds industry-grade SystemVerilog and VHDL parsers.

How can I learn what synthesis produces?

Build small circuits by hand and compare: a 2-to-1 multiplexer, an adder and a D flip-flop are the cells a synthesizer maps most code onto. digiwleea lets you build each from gates and watch it work.