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Microwind and DSCH alternative: CMOS logic in your browser

Microwind is CMOS design software for education, from Toulouse, France, now at version 3.9: a layout editor and simulator that takes a chip from schematic to layout to simulation in one flow, with technology files down to FinFET (since 3.8) and nanosheet FETs (3.9, with a 3 nm rule file). It comes with DSCH, a logic editor and simulator that its site describes as the place to validate a logic architecture before the microelectronics design starts: hierarchical schematics, fast simulation with delay analysis, stuck-at fault injection, export to a SPICE netlist (PSPICE and WinSpice compatible) or Verilog, and models for the 8051 and PIC16F84 microcontrollers. Downloads require signing in on microwind.net. If what you want is to learn how CMOS transistors make logic, digiwleea covers that first step in the browser, with nothing to install.

What Microwind and DSCH are good at

Teaching real chip design. Microwind lets students draw transistor layouts in actual process technologies, work with real process rules, and simulate the extracted circuit, so they learn why a NAND gate's layout looks the way it does and how scaling changes speed and power. DSCH adds the logic level, with delays and fault testing. Together they cover the VLSI course from gate to silicon. (digiwleea is an independent project, not affiliated with Microwind or ni logic.)

How digiwleea is different

digiwleea stays at the schematic and logic level: you place NMOS and PMOS transistors as switches (every wire is 0, 1 or floating), build NOT and NAND, and go up through adders, latches, registers, RAM and an 8-bit CPU that runs a stored program, plus the assembly language behind it, through a 40+ level course where every part is checked against its truth table, with an AI tutor (Wleea). It has no layout, process technologies, parasitics or timing, so for a VLSI layout course Microwind is the right tool. It runs in any browser, which makes it a quick way to get the switch-level picture before layout. For the industrial flow, see the Cadence Virtuoso comparison.

Microwind and DSCHdigiwleea
LevelLayout and process technology (Microwind); logic with delays (DSCH)Transistors as switches, gates and up to a CPU
SimulatesExtracted layouts with parasitics; logic with timing and faultsSwitch-level logic: 0, 1 and floating, no timing
Runs onDesktop software, downloaded after signing inAny modern browser, nothing to install
Learning pathApplication notes and tutorials for VLSI coursesA 40+ level course from transistor to CPU, with an AI tutor
PriceCommercial education softwareFree lab and Act I; Premium for the full course

The CMOS basics, live

No sign-up is needed to start: open the lab and place your first transistor, or read the free theory course. The account (and the AI tutor) are optional.

More comparisons: HDL, FPGA and chip design tools

See for yourself: build a logic gate from transistors in the simulator, then follow the path from sand to an 8-bit CPU.

Open the digiwleea lab →

Frequently asked

What is Microwind used for?

Teaching and practising CMOS integrated-circuit design: drawing transistor layouts in real process technologies, checking them, and simulating the extracted circuits. Version 3.9 adds nanosheet FET technology.

What is DSCH?

The logic editor and simulator that comes with Microwind. It validates a logic design with delay analysis and fault injection before layout, and exports SPICE netlists and Verilog.

Is there an online alternative to Microwind?

For transistor layout, Microwind and desktop VLSI tools remain the options. For the switch-level side (how CMOS transistors make gates and how gates make a CPU), digiwleea runs in the browser with a free lab.