CMOS full adder: the 28-transistor mirror adder, live

The classic CMOS full adder is the 28-transistor mirror adder: a 10-transistor stage computes NOT Cout, a 14-transistor stage uses it to compute NOT S, and two inverters (4 transistors) give S and Cout. This live circuit is built transistor by transistor and checked on all eight rows.

Built from separate static CMOS gates, a full adder (two XORs, two ANDs and an OR) takes about 42 transistors with 12-transistor XORs and 6-transistor ANDs and ORs. The mirror adder does it in 28 by computing the outputs directly as transistor networks. The carry stage is the majority gate's mirror circuit: Cout = A B + Cin (A + B), so NOT Cout pulls low through A and B in series, or through Cin in series with A or B. The sum uses the carry: S = A B Cin + (A + B + Cin) NOT Cout, which is 1 when all three inputs are 1, or when at least one is 1 and there is no carry (exactly one input is 1). So NOT S pulls low through A, B and Cin in series, or through any of A, B, Cin in series with a transistor driven by NOT Cout. Both functions are self-dual, so each pull-up network has the same series and parallel shape as its pull-down (a mirror, hence the name) instead of the complementary one, which keeps the PMOS stacks short. Compare the full adder from gates and the nine-NAND full adder.

Big circuit: pinch, scroll or tap + to zoom in, then drag to move around.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

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<iframe src="https://digiwleea.wleeaf.dev/embed/?c=H4sIAAAAAAAAA42bS4_buBJG_4vWDiCS4su7O7Oa9SwHWTjdnsC4HXfQj8lcBPnvF51Ycn3UYVu7BqFDVpGfqopl9ffh78enL4eXYT_cnz6fvj0cj4cPd6enu9fTy7Ab_jk-PZ8ez8Pe7Ybz4ctx2A93Xx6fP_z9-vDw4XB_f3wadsP5-O_LH_fD3sdpN5zOzy-H893xedj_9X043b8RbtgN_z2d3_7-5-5u2A2PT6fPp_Ow_z78O-yn3fC_YZ9-7Ianx5fDy8_lxh-7GfZX-PP5nuFQenS40qfz19cX5t2k_G54OHw6Pgz74T9vm3B4eD3KrNOmWb3vzfobzho3zRrG3qy_n844b7rO-_Xp8dOxndfVfGMX_hyus-WNs6WumY-vL2a-cp3v_OXxuZ2uuJ-z1al3wtXY0-e78nLjpvWdG7szuE0WtGowE_htJoz9GcImE9oDNhNMG3eh-6K5uMmEVr1mgrTNBN8_yrzNhL4P27ToQn8ft6lx6ke7jXKM3X302-SYumLyG-WY-k5sk2PuHoTfKMep78Q2OcbuSfqNcox9J7bJMfdPcqMcc9-JbXIs3ZMMN-To8i1BhxtynGfoh8fgt83QNyFsc6Ifm8K0zYR-gA1xow2tnD7uhm-nJ1tOfQtv0jzMR3iR4Y_d8GmuE-I8tqz_LWTLXHJqXkM1W6gABIxF6hpxI1k3WvOmETAwz1nzJgdQICoI5tfYBG5N1q8pwFoT-TWJX9Mai2BhFAOjgZY9vrXSWhQ-WCjNY4YBUTgH1NugwUAWPsJaYh8JwztYyzuDRRBGAAuDNTCSMCL5FQUDYSTwK1m_IgkjkV9J_AJhZLAwi4EijNQ95GaptTKC2JfnMcOQMnxdU2-DBgNlTLDWJGuRMhKtlexaCZRRYK1i10qkjJxhrWzfyATKKGBhEQOtMq6bfGspEcblejqOBlsGxbFImF2tFMJEG-U9bLRYJkyMTIQVMNKhb7KRlXyrZKTF8khGEuaskdkB5sg3xUQi6Z0tUSysfft51212pNo4kEEj1caBkgESheQ-NFkoAWTNc74AleHAft7b2nOWFJFJHpJY5uNQrMKBMZYMVkgeYuTsW8O5tZW-rH2TwFg8QHW9-QqF9eYjVCw0AVTAK6UgfEwgQyk5SgIoru1TKK_tQ8gKqhSASIZKWWEsN5VKmN32OgImelq20DpWHWC0mKzlAZL6ZqakwKlWGdd5b0m3Um4JHt5LXY1yS4DQ0WAQOzqYtxgFj9EDNgqGuQXeSyd3iEq5RW4eSwqwmBspejBXhMPsUsC7hvOwmbgrspluhPzi8MSFQqHQYkJBhkFKLSSZeIreQoFKPPgllwk3gkjkDjIHTKUqhFSixEI3AgV-NRTp4zZF6UVqjzqPWQq0ESBLy-3ZOdCGXLovvjYUaAOpJBRoQy2sRIE2QgFK3jAn2qjdPWwoih8TlbRy53F-JA5E1XIO3hbm5Kw9xQ-xs47IUfyI6F8VjiLIBMVLy1EMQS6qnRRFIvnXcFYrZgtucpRuIpW40tpxnvQS4UVouADRpMPJuxBIL2JndchBRPnV8W_9k26IC6SXBPVdy0HZ2uHUTtJLIv8azurFbMFNjqqToKVoXUYtaAXj8qValuvGPKgbU4mTajRV4KSjah4BThyUpqp5ZO1gw4FgCtwgiloJcilw6g0FYkFKTmACqRQ6uQZLcAB6o5oHJZJJc9U8sj6AhitwAMxJJpIGq3lk7Z9yka47UskuipaIFOm-I5loEYpkMOmymqlvvkHSaZ03NHo4COnqOmm1mkfWG9pwETaUOSnGpN9qHjFcGImj0DIR9zZqQcxFhcCoR0_JKMNL66QN7RIVL5kq_YajZMScnHyi4kXsXBxsQJHMdddvg1C-RLheqGKoCRvBvYaC0gUpOfQEfRSxsHqiQCoJ_JIfEBw1YBPUnEplKFmQEgszaCSBXw1lFXL1_BYF2SdBy0B-d3DUfU1QoTYUZB-k5A2l_qtYWANREEky-CU_PDhqv2aoMBsKLsdIiYUFtJHBr4ay2rh6fouCyiSNEgPcPGgxEEdOgGWpgwr15j1gVaQoDdilWqDkpr2JgtWJg_UaTqqT6yPAqZ2FuA3-URnryD_tKTXNWGhFuVyI0-qkvMOJnU1DFhowbv4dRznJNJdPIDNg8vJUKk3CCFgQbUpH9jrzTQzFosvledByGZyTT07ccrUUju48gUpnbRZVEot0i-aTEc6PIxwec0U4EovaOTeflBOxlHf2peGsWH59zGEXW39V46Uhu_4ixANhJeI7hFqVVkRZEZMQkGegRRCFgSwjOzY6gEQQyxNrSsxz2GMTys-DFhM1XB9Zc4pBmtFXeQzrd9JLE9Y8suZ0NUgzeksfl0GLSeAY3-MEg1_6ou5InActJnHj-siaU4wKEd2RNA9aTEWS-pysRp3YojuS50GLqUpyn9PVPIQ26gKJ_j1efSGuKTVBWCNKLaRKROWfK7w2XpNL7XOK5VXUuc3gb33SvLsOWs4qpL7D2dTupfUa17khQiaStuvyQBtMG8avdoIYidnSbvVr2wIxVhahx-gW4NdFUnnHZdBy0mWNfU5Xw89HrCpqWgYtZ2VhHllxuho2QeTumJdBw0mD1Tyy4pSCr0fcJDtSlkHLyQW39DldDbvxsiN1GbSclYh5ZMXpaqSSQr8VyTd5foLs4uRTPjeOCGp-Gd8lJVdok9U8sybVRaxMNX6nedBwTZM19TlZrumxwnc5LsPnMl57rNdH1pwuF1aRwTPzcTc8nz6fDw-_vku__Gtg-89yl-H2v90uw82_q3388X-5u9KejDgAAA" width="100%" height="560" style="border:0;border-radius:12px;max-width:640px" title="28-transistor CMOS full adder circuit (digiwleea)" loading="lazy"></iframe>

To cite it: digiwleea, “28-transistor CMOS full adder”, https://digiwleea.wleeaf.dev/tools/build/cmos-full-adder/

What you need

5× NMOS: carry stage pull-down: A series B, parallel to Cin series (A parallel B)
5× PMOS: carry stage pull-up, the same shape
7× NMOS: sum stage pull-down: A series B series Cin, parallel to (A parallel B parallel Cin) series NOT Cout
7× PMOS: sum stage pull-up, the same shape
4× NMOS + PMOS: two inverters: NOT Cout to Cout, NOT S to S

Step by step

Place a VDD rail, a GND rail, inputs A, B and Cin, and probes S and Cout.
Carry stage, to a node NC: NMOS A and B in series to GND, in parallel with NMOS Cin in series with NMOS A and B in parallel; the PMOS pull-up from VDD has the same shape. NC is NOT Cout.
Sum stage, to a node NS: NMOS A, B and Cin in series to GND, in parallel with an NMOS gated by NC in series with NMOS A, B and Cin in parallel; the PMOS pull-up from VDD has the same shape. NS is NOT S.
Invert NC to get Cout and NS to get S, then step through all eight rows.

Full adder truth table

A	B	Cin	NOT Cout	Cout	S
0	0	0	1	0	0
0	0	1	1	0	1
0	1	0	1	0	1
0	1	1	0	1	0
1	0	0	1	0	1
1	0	1	0	1	0
1	1	0	0	1	0
1	1	1	0	1	1

All eight rows of the live circuit are checked against A + B + Cin before the page is built. In every row exactly one network of each stage conducts, so no node floats and nothing shorts. The two-input version is the 16-transistor CMOS half adder.

You can also read the full theory in the lesson on the full adder. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

More builds: Gates from transistors (CMOS)

CMOS half adder (16 transistors)CMOS inverter CMOS majority gate CMOS NAND gate CMOS AOI gate (AOI21)CMOS NOR gate 4-to-1 mux from transmission gates CMOS AND gate 2-to-1 mux from transmission gates CMOS OR gate tri-state buffer (CMOS)CMOS XOR gate

All 246 build guides, by topic

Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the 28-transistor CMOS full adder in the lab →

Frequently asked

How many transistors are in a CMOS full adder?

The standard mirror adder uses 28: 10 for the carry stage, 14 for the sum stage and 4 for the two output inverters. Built from separate static CMOS gates instead (two 12-transistor XORs, two ANDs and an OR), it takes about 42.

What is a mirror adder?

A CMOS full adder whose pull-up networks have the same series and parallel structure as their pull-down networks, possible because the carry and sum functions are self-dual. It reuses NOT Cout in the sum stage and keeps PMOS stacks short.

Why does the sum stage use the carry?

Because S = A B Cin + (A + B + Cin) NOT Cout: the sum is 1 when all three inputs are 1, or when some input is 1 but there is no carry. Reusing the carry signal saves transistors compared with two XOR stages.

Why are the outputs inverted inside the mirror adder?

A single static CMOS stage can only compute an inverting function, so each stage produces NOT Cout or NOT S, and an inverter restores the true output. In ripple-carry chains, designers often skip the carry inverter and alternate polarities between stages to save delay.