CMOS half adder: 16-transistor circuit, live

A half adder in CMOS is a complementary XOR gate for the sum and a NOR gate for the carry, 16 transistors in all. The XOR's two input inverters already make A' and B', and C = AB = NOR(A', B'), so the carry needs only four more transistors.

A half adder adds two bits: S = A XOR B and C = A AND B. The sum is the 12-transistor CMOS XOR gate: two inverters make A' and B', the NMOS pull-down network (A series B) parallel (A' series B') pulls S to 0 when the inputs are equal, and the PMOS pull-up network, its dual, pulls S to 1 when they differ. For the carry, the obvious choice is a CMOS AND gate, a NAND plus an inverter, 6 transistors. But by De Morgan's law AB = (A' + B')' = NOR(A', B'), and A' and B' are already there, so a 4-transistor NOR gate (PMOS in series, NMOS in parallel) gives the carry directly: 16 transistors instead of 18. Every output is driven by a static CMOS stage, so S and C are always a full 0 or 1. The same idea one step up is the 28-transistor CMOS mirror full adder, and the gate-level version is the half adder with one XOR and one AND.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

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To cite it: digiwleea, “CMOS half adder (16 transistors)”, https://digiwleea.wleeaf.dev/tools/build/cmos-half-adder/

What you need

2× CMOS inverter: A' and B' (4 transistors), shared by the sum and the carry
1× complementary XOR network: S = A XOR B: 4 NMOS pull-down, 4 PMOS pull-up (8 transistors)
1× CMOS NOR: C = NOR(A', B') = AB (4 transistors)

Step by step

Place inputs A and B, VDD and GND, and probes S and C.
Build two CMOS inverters for A' and B'.
Sum: NMOS A and B in series, in parallel with NMOS A' and B' in series, from S to GND; PMOS A and B in parallel, in series with PMOS A' and B' in parallel, from VDD to S.
Carry: PMOS A' and B' in series from VDD to C, NMOS A' and B' in parallel from C to GND.
Toggle A and B: S is 1 when exactly one input is 1, C only when both are.

CMOS half adder truth table

A	B	A'	B'	S = A XOR B	C = NOR(A', B')
0	0	1	1	0	0
0	1	1	0	1	0
1	0	0	1	1	0
1	1	0	0	0	1

All four rows of S and C are checked on the live circuit before the page is built, and the circuit is transistors only.

You can also read the full theory in the lesson on the half adder. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

More builds: Gates from transistors (CMOS)

CMOS majority gate 28-transistor CMOS full adder CMOS AOI gate (AOI21)CMOS inverter 4-to-1 mux from transmission gates CMOS NAND gate 2-to-1 mux from transmission gates CMOS NOR gate tri-state buffer (CMOS)CMOS AND gate CMOS transmission gate CMOS OR gate

All 246 build guides, by topic

Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the CMOS half adder (16 transistors) in the lab →

Frequently asked

How many transistors are in a CMOS half adder?

Sixteen in this design: 12 for the complementary XOR (including the two input inverters) and 4 for a NOR gate that makes the carry from the inverted inputs. With a separate 6-transistor AND gate for the carry it would be 18.

How do you design a half adder using CMOS?

Make the sum with a static CMOS XOR gate and the carry with a CMOS AND, or more cheaply with a NOR gate fed by the XOR's inverted inputs, since AB = NOR(A', B').

Why is the carry a NOR gate?

De Morgan's law: NOT(A' + B') = AB. The XOR already needs A' and B', so a 4-transistor NOR of those two signals gives A AND B without a separate NAND and inverter.

What is the difference between a CMOS half adder and a full adder?

A half adder adds two bits and has no carry input. A full adder adds three, A, B and a carry-in; the CMOS mirror full adder does that in 28 transistors.