Majority gate: a 3-input majority function in 12 transistors

A majority gate outputs 1 when most of its inputs are 1: with three inputs, Y = A B + B C + A C, so Y is 1 whenever at least two of A, B and C are 1. This live circuit builds it from 12 CMOS transistors, a 10-transistor stage that computes NOT majority and an inverter.

The 3-input majority function is everywhere once you look for it. It is the carry out of a full adder: a column of A + B + Cin carries exactly when at least two of the three are 1. It is the voter in triple modular redundancy, where three copies of a circuit run side by side and the majority of their outputs wins, so one faulty copy is outvoted. As gates it takes three 2-input ANDs and a 3-input OR, or four NANDs: NAND(NAND(A, B), NAND(B, C), NAND(A, C)). In CMOS it fits in one stage plus an inverter. Majority is self-dual (inverting all three inputs inverts the output), so the pull-up network can use the same series and parallel shape as the pull-down network instead of its mirror image, which is why this design is called a mirror circuit. It is the carry stage of the classic 28-transistor mirror adder. Probe NY shows the inverted stage's output and Y the majority itself.

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Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

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To cite it: digiwleea, “CMOS majority gate”, https://digiwleea.wleeaf.dev/tools/build/majority-gate/

What you need

5× NMOS: the pull-down network: A and B in series, in parallel with C in series with (A parallel B)
5× PMOS: the pull-up network, the same shape: A and B in series, in parallel with (A parallel B) in series with C
2× NMOS + PMOS: the output inverter that turns NY into Y

Step by step

Place a VDD rail, a GND rail, inputs A, B and C, and probes NY and Y.
Pull-down network from NY to GND: NMOS A and NMOS B in series (any two of A and B), and in parallel with it NMOS C in series with a parallel pair of NMOS A and NMOS B (C plus either of the others).
Pull-up network from VDD to NY, the same shape in PMOS: PMOS A and PMOS B in series, in parallel with a parallel pair of PMOS A and PMOS B followed by PMOS C. It conducts when at least two inputs are 0.
Add a CMOS inverter from NY to Y, then step through all eight rows: Y is 1 exactly on the four rows with two or three 1s.

Majority gate truth table

A	B	C	Ones	NY	Y
0	0	0	0	1	0
0	0	1	1	1	0
0	1	0	1	1	0
0	1	1	2	0	1
1	0	0	1	1	0
1	0	1	2	0	1
1	1	0	2	0	1
1	1	1	3	0	1

Y is 1 on four of the eight rows, the ones with at least two 1s. It is also the Cout column of the full adder's truth table, with C as the carry in. Every row has exactly one network conducting: the pull-down when at least two inputs are 1, the pull-up when at least two are 0. Another three-input gate with a special role is the reversible Toffoli gate.

You can also read the full theory in the lesson on designing CMOS gates from truth tables. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

More builds: Gates from transistors (CMOS)

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All 246 build guides, by topic

Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the CMOS majority gate in the lab →

Frequently asked

What is a majority gate?

A logic gate whose output is 1 when more than half of its inputs are 1. The 3-input version computes Y = A B + B C + A C, so it is 1 whenever at least two of the three inputs are 1.

How do you make a majority gate from logic gates?

With three 2-input AND gates (A B, B C and A C) feeding a 3-input OR gate, or with four NAND gates: three 2-input NANDs on the pairs and a 3-input NAND that combines them. In CMOS, a single 10-transistor stage computes NOT majority and an inverter gives the majority, 12 transistors in all.

Is the carry of a full adder a majority function?

Yes. A full adder's carry out is 1 exactly when at least two of A, B and Cin are 1, which is the majority of the three. That is why the mirror adder's carry stage is a majority gate.

What is a majority gate used for?

Carries in adders, and voting in fault-tolerant systems: triple modular redundancy runs three copies of a circuit and passes on the majority of their outputs, so a single fault is outvoted. Majority is also the basic gate of some emerging technologies, such as quantum-dot cellular automata.

Why is the majority gate self-dual?

Inverting all three inputs inverts the output: if at least two inputs are 1, then after inverting at least two are 0, so the majority flips. For a self-dual function the pull-up and pull-down networks of a CMOS gate can have the same shape, which is what makes the mirror design possible.