CMOS XNOR gate: twelve transistors, live

A static CMOS XNOR gate uses twelve transistors: two inverters make NOT A and NOT B, and an eight-transistor complex gate pulls the output low when A and B differ and high when they are equal, so Y is 1 exactly when A = B.

The pull-down network has two NMOS paths from Y to ground: A in series with NOT B, and NOT A in series with B. One of them conducts exactly when A and B differ, giving Y = 0. The pull-up network is its dual: PMOS on A and NOT B in parallel, in series with PMOS on NOT A and B in parallel, which conducts exactly when A = B. It is the CMOS XOR with NOT B and B swapped in both networks, so it costs the same twelve transistors, two fewer than an XOR followed by an inverter. Equality checks are where XNOR earns its keep: a 1-bit comparator's EQ output is an XNOR, and an n-bit equality test is n XNORs feeding an AND. Compare the gate-level truth table on the XNOR truth table page.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

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<iframe src="https://digiwleea.wleeaf.dev/embed/?c=H4sIAAAAAAAAA42Zy27jOBBF_4VrNSC-Re-md_MJg0YWjuMJhHHkhu100gj874O4paiu69LyLijw1IuXRYX-MP_uDy_rk1mZp_65f9ttt-tvm_6wee1PpjG_todjvx_MyjZmWL9szcpsXvbHb-_D_mAaM2zfT38_mZV1pTH9cDyth832aFY_Pkz_9LnWmsb81w-ff__abExj9of-uR_M6sO8m5UNjfltVvHcmMP-tD5dIrXnZqLdTD8PTxU6tDXcz3g__Hw9XTv4w9ur8I3ZrR-3O7Myf302YL173YLXcJdX72pev1Ovcfb687B_3F57jfbi1vma23_M7CwJZy_7o2pcvvjqan3LMz7UcZdqfHc7vFsIX26Hd0vhbXs7vl-Ib-1tPvgF3t0V39YL8HclcMNBuN1Cv9jCeJcDH6oO0m0HYwk3MlgQ4ehAZfDQmLf-IGfQm_3U43oSb7xw-dyYRzSl81f0N1sE4tqv_X5Ek0RcKxCvEU8QK5CgkUAQJ5GkkaQRr8tPC0jQ5V8G2lX9wUoo6jiX2XzVZ4SS7hpE8ixS1n2DSIFBne4cQolAhdRkFyAvldDNR3ViymQSiFRCqSJeIk4jXiAdQbxOTCNBElII49y3sn7rJ5uAQAi-CkFqSTMytTE2IFnnRhAop9OIK5JJk01AoIFUh6KAQkugKE-QJ5BUwbxAQVkyTjNZdwEQr7tAENm4IHXgiQ480UGQOvBEB6MNWpA0IzswxgYk69wIAuV0GoEt9UQHQerAEx2MNhko6lEQbqcWrR69NujRa2ULoiMQCCcQSMrAhToE6QUCQXqOQFII8wIFydMdky7JJd0HB4EygYIuCaFOl0QhObBjIVDSJQGUWt0HBsk-JEtOHqguTjYBST3MCxQEgaQcps8zyQSnz0SScpgXKAgCETX4BSSpY-QlkieTQKQUskY8QWAq1BAniaIIp9KSQAYFkDnqkp6jGUZCqkOScYSRSNaIJ7lpBMoJGoHtd1FrJsP-xyokZ1VOmok6N0Cyzo0gUE6njwAcm2D1WctSA_MCBclAXasDeXkF-zLZBASToNQhqenOEUiKOrYEkkqYFyhItrsLmok6OUCizo0g0LikTrVbaDV8HZD71JP7tOsIBKl5AsEw8HVIXj6lJRCkR-7TAkog9-lkk4zTJcHdM9lkScUTiJSEUNAlUUhejYV8K2J65D4tSfeBQdCHTM44_EfnNUM-F_HkBX1cC8ghVCEZyLYt2dnbydmWvCI4OBWjzQPlCAXXcGEUfCSUOuWACoSCDDtGSUnMKxTVAiQlMf5zfkco8qAAQgrkcNi2I1QkzUCqkGYwCt6jbEuoROpCypIWEgpaaMkTkyMPRvARba0nFMykyCiYFbFKBdguGzUVyCZfUUk3g1FXLZTSmB7hZYajDVvY6VDtElO0mmCoB3JRWXh1DOSmGrVyRVmtJkrBZuHbYyEZZkYRYdxBBVJXIhRsFjxBTrGWKRBGrmeIFJkZnoxdj3WRV0ik0hf10Jhj_zysd38es8ef365_lBrN8KvSw_l_QPAN19cbAAA" width="100%" height="420" style="border:0;border-radius:12px;max-width:640px" title="CMOS XNOR gate circuit (digiwleea)" loading="lazy"></iframe>

To cite it: digiwleea, “CMOS XNOR gate”, https://digiwleea.wleeaf.dev/tools/build/cmos-xnor/

What you need

2× CMOS inverter (1 PMOS + 1 NMOS): NOT A and NOT B
4× NMOS transistor: pull-down: (A series NOT B) in parallel with (NOT A series B)
4× PMOS transistor: pull-up: (A parallel NOT B) in series with (NOT A parallel B)

Step by step

Place a VDD rail, a GND rail, inputs A and B, and a probe Y; build two CMOS inverters for NOT A and NOT B.
Pull-down: NMOS A in series with NMOS NOT B from Y to GND, and in parallel NMOS NOT A in series with NMOS B. Either path conducts when A and B differ.
Pull-up: PMOS A and PMOS NOT B in parallel from VDD to a middle node, then PMOS NOT A and PMOS B in parallel from that node to Y. It conducts when A and B are equal.
Step through the four rows: Y is 1 for 00 and 11, and 0 for 01 and 10.

CMOS XNOR truth table

A	B	Pull-down on	Pull-up on	Y
0	0	no	yes	1
0	1	yes	no	0
1	0	yes	no	0
1	1	no	yes	1

All four rows of the live circuit are checked before the page is built. In every row exactly one of the two networks conducts, so Y is always driven and VDD never connects to GND.

You can also read the full theory in the lesson on XOR at the transistor level. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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All 246 build guides, by topic

Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the CMOS XNOR gate in the lab →

Frequently asked

How many transistors are in a CMOS XNOR gate?

Twelve in this static design: four for the two input inverters and eight for the complex gate. Transmission-gate and pass-transistor versions use fewer, at some cost in drive strength.

What is the difference between a CMOS XOR and XNOR?

They use the same structure; the XNOR swaps B and NOT B in both networks, so its output is high when the inputs are equal instead of when they differ.

Why is XNOR called an equality gate?

Because its output is 1 exactly when its two inputs are equal. Comparators use one XNOR per bit and AND the results to test whether two numbers are equal.