4:1 mux using transmission gates: 16-transistor circuit, live

A 4-to-1 multiplexer can be built from six transmission gates arranged as a tree: four on the first level, steered by S0, pick D0 or D1 and D2 or D3, and two on the second level, steered by S1, pick between those results. With two inverters for S0' and S1' that is 16 transistors, against dozens for a mux built from NAND gates.

A transmission gate is an NMOS and a PMOS transistor in parallel, driven by complementary signals, so it passes both a strong 0 and a strong 1 when it is on and disconnects when it is off. A pair of them on S and S' is a 2-to-1 mux: exactly one conducts, so the output is never left floating. The 4-to-1 mux reuses that pair three times. On the first level, S0 = 0 connects D0 and D2 to the two intermediate nodes and S0 = 1 connects D1 and D3. On the second level, S1 = 0 connects the D0/D1 node to Y and S1 = 1 the D2/D3 node. The selected input reaches Y through two transmission gates in series, which is why larger pass-transistor trees are usually broken up with buffers: each switch adds resistance and slows the signal. Only the two inverters are tied to the supply. The 2-to-1 version is the transmission gate mux, a single gate is the transmission gate, and the same tree built from logic gates is the 4-to-1 mux from 2-to-1 muxes.

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Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

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To cite it: digiwleea, “4-to-1 mux from transmission gates”, https://digiwleea.wleeaf.dev/tools/build/transmission-gate-mux-4to1/

What you need

4× transmission gate: first level, S0 and S0': D0 or D1, and D2 or D3 (8 transistors)
2× transmission gate: second level, S1 and S1': the D0/D1 result or the D2/D3 result (4 transistors)
2× CMOS inverter: S0' and S1' (4 transistors)

Step by step

Place inputs D0 to D3, S1 and S0, a probe Y, and VDD and GND for the two inverters.
Invert S0 and S1 with two CMOS inverters.
First level: transmission gates pass D0 when S0 = 0 and D1 when S0 = 1 onto one node, and D2 or D3 onto a second node the same way.
Second level: a transmission gate passes the first node to Y when S1 = 0, and another passes the second node when S1 = 1.
Set S1 S0 to 00, 01, 10 and 11 and toggle the selected data input: Y follows it.

4:1 transmission gate mux: which path conducts

S1	S0	First level on	Second level on	Y
0	0	D0 and D2 gates	D0/D1 node	D0
0	1	D1 and D3 gates	D0/D1 node	D1
1	0	D0 and D2 gates	D2/D3 node	D2
1	1	D1 and D3 gates	D2/D3 node	D3

All 64 combinations of the four data inputs and two selects are checked on the live circuit before the page is built, and the circuit is transistors only.

You can also read the full theory in the lesson on the transmission gate. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

More builds: Gates from transistors (CMOS)

2-to-1 mux from transmission gates CMOS AOI gate (AOI21)tri-state buffer (CMOS)CMOS majority gate CMOS transmission gate CMOS half adder (16 transistors)CMOS XNOR gate 28-transistor CMOS full adder CMOS XOR gate CMOS inverter CMOS OR gate CMOS NAND gate

All 246 build guides, by topic

Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the 4-to-1 mux from transmission gates in the lab →

Frequently asked

How do you design a 4:1 mux using transmission gates?

Build a tree of 2-to-1 transmission gate muxes: four transmission gates controlled by S0 and S0' choose D0 or D1 and D2 or D3, then two more controlled by S1 and S1' choose between those two results. Two inverters make S0' and S1'.

How many transistors are in a 4:1 transmission gate mux?

Sixteen: six transmission gates of two transistors each, plus two CMOS inverters for S0' and S1'.

Why use transmission gates instead of single NMOS pass transistors?

An NMOS pass transistor passes a strong 0 but a weak 1, and a PMOS the opposite. With both in parallel, a transmission gate passes full 0 and 1 levels.

What are the drawbacks of transmission gate logic?

The inputs drive the output through the switches, so each gate in series adds resistance and delay, and the signal is not restored. Long chains are broken up with buffers or inverters.