Verilog vs VHDL: what is different, and which to learn

Verilog and VHDL are the two classic hardware description languages: text that describes digital circuits so they can be simulated and synthesised into gates on an FPGA or a chip. Verilog was standardised as IEEE 1364, whose last edition (1364-2005) has been superseded by SystemVerilog, IEEE 1800, now in its 2023 edition, which models hardware at the behavioral, register-transfer and gate levels and adds testbench features such as coverage, assertions, object-oriented programming and constrained random verification. VHDL is IEEE 1076, currently 1076-2019, which the IEEE describes as a formal notation for all phases of creating electronic systems, readable by both machines and humans. The short answer: they describe the same hardware, so learn the one your course, team or FPGA vendor examples use; the ideas carry over.

What each one is good at

Verilog is compact and C-like, so small designs are quick to write and read, and SystemVerilog extends the same language into large verification environments. VHDL is strongly typed and explicit, which catches many mistakes at compile time and makes intent clear in big, long-lived designs. Both are supported by the main FPGA tools, and both have free simulators: Icarus Verilog and Verilator for Verilog, GHDL for VHDL, compared on our HDL simulators page. (digiwleea is an independent project, not affiliated with the IEEE.)

Where digiwleea helps

Either language is easier once you know what the code becomes. In digiwleea you build the circuits themselves, multiplexers, adders, flip-flops, registers and a small CPU, from transistors up in the browser, and the free lessons then describe them in both languages: start with what an HDL is, VHDL entities and architectures and Verilog modules. The lab can export a circuit as VHDL and build a combinational circuit from a short VHDL description. To run larger HDL designs, use a simulator such as EDA Playground or Questa.

Verilog and VHDL side by side

	Verilog	VHDL
Standard	IEEE 1364 (last 1364-2005), superseded by SystemVerilog, IEEE 1800 (current 1800-2023)	IEEE 1076 (current 1076-2019)
Syntax	Compact, C-like: modules, assign, always blocks	Verbose, Ada-like: entity, architecture, process
Typing	Loose: a few net and variable types, many implicit conversions	Strong: every signal has a type, conversions are explicit
Verification	SystemVerilog adds assertions, coverage, classes and constrained random testbenches	Testbenches in VHDL itself
Free simulators	Icarus Verilog, Verilator	GHDL

The same 2-to-1 multiplexer in both

Verilog:

module mux2(input a, input b, input s, output y);
  assign y = s ? b : a;
endmodule

VHDL:

library ieee;
use ieee.std_logic_1164.all;

entity mux2 is
  port (a, b, s : in std_logic; y : out std_logic);
end entity;

architecture rtl of mux2 is
begin
  y <= b when s = '1' else a;
end architecture;

Both describe the same hardware: when S is 1 the output follows B, otherwise A. Build it from gates and watch it switch in the live 2-to-1 multiplexer.

No sign-up is needed to start: open the lab and place your first transistor, or read the free theory course. The account (and the AI tutor) are optional.

More comparisons: HDL, FPGA and chip design tools

Tiny Tapeout Verilog vs SystemVerilog KLayout alternative Blocking vs nonblocking Cadence Virtuoso alternative Python and Scala HDLs compared Magic VLSI vs Electric VLSI WaveDrom alternative IRSIM alternative EDA Playground alternative Microwind alternative HDLBits alternative

See for yourself: build a logic gate from transistors in the simulator, then follow the path from sand to an 8-bit CPU.

Open the digiwleea lab →

Frequently asked

Should I learn Verilog or VHDL first?

Learn the one your course, team or target FPGA's examples use; the hardware ideas are the same, and moving to the other later is mostly syntax and typing. Verilog is shorter to write; VHDL's strict typing catches more mistakes early.

Is Verilog the same as SystemVerilog?

SystemVerilog, IEEE 1800, superseded the Verilog standard IEEE 1364 in 2009. It contains Verilog and adds features, most of them for verification: assertions, coverage, classes and constrained random testbenches.

Is VHDL still used?

Yes. VHDL is an active IEEE standard (IEEE 1076-2019), supported by FPGA tools and by the free GHDL simulator.

Which is easier, Verilog or VHDL?

Verilog is usually quicker to start with because its syntax is compact and C-like. VHDL is more verbose, but its strong typing makes errors clearer. Either is easier once you have built the circuits by hand.