Verilog vs SystemVerilog: what SystemVerilog adds

SystemVerilog is the successor to Verilog. The Verilog standard, IEEE 1364, was last revised in 2005 and was superseded in 2009 by IEEE 1800, SystemVerilog, now in its 2023 edition. SystemVerilog contains Verilog, so most Verilog code is valid SystemVerilog, and it adds two kinds of features: design features that make hardware intent explicit, such as the logic type and the always_comb and always_ff blocks, and a large verification language, which the IEEE describes as testbenches using coverage, assertions, object-oriented programming and constrained random verification. For writing hardware, SystemVerilog is Verilog with clearer intent; for testing hardware, it is a much bigger language.

What each one is good at

Plain Verilog is small and widely supported, which is why many courses and free tools start there: Icarus Verilog aims at the IEEE 1364 language with a growing subset of SystemVerilog. SystemVerilog is what most new design and verification work uses: always_ff and always_comb let tools catch blocks that would not become the hardware you meant, interfaces bundle buses, and the verification features power methodologies such as UVM. Verilator accepts Verilog and SystemVerilog, including UVM; our HDL simulators page compares them, and Verilog vs VHDL covers the other language.

Where digiwleea helps

Both languages describe the same gates and flip-flops, and digiwleea is where you build those by hand, from transistors up, before writing them as code. The free Verilog lessons then describe the course circuits, from modules and continuous assignments to clocked always blocks and testbenches. To run SystemVerilog, use a simulator such as EDA Playground or Questa; digiwleea does not simulate HDL code.

Verilog and SystemVerilog side by side

	Verilog	SystemVerilog
Standard	IEEE 1364 (last 1364-2005)	IEEE 1800 (superseded 1364 in 2009; current 1800-2023)
Design	Modules, wire and reg, always blocks	Adds the logic type, always_comb and always_ff, interfaces
Verification	Basic testbenches	Assertions, coverage, classes, constrained random testing
Free simulators	Icarus Verilog, Verilator	Verilator (including UVM); Icarus covers a growing subset

The same D flip-flop in both

Verilog:

module dff(input clk, input d, output reg q);
  always @(posedge clk) q <= d;
endmodule

SystemVerilog:

module dff(input logic clk, input logic d, output logic q);
  always_ff @(posedge clk) q <= d;
endmodule

always_ff states that this block is meant to become flip-flops, so tools can check it and warn when the code would not produce them. Build the flip-flop itself in the live D flip-flop.

No sign-up is needed to start: open the lab and place your first transistor, or read the free theory course. The account (and the AI tutor) are optional.

More comparisons: HDL, FPGA and chip design tools

Verilog vs VHDL Blocking vs nonblocking Tiny Tapeout Python and Scala HDLs compared KLayout alternative WaveDrom alternative Cadence Virtuoso alternative EDA Playground alternative Magic VLSI vs Electric VLSI HDLBits alternative IRSIM alternative ModelSim alternative

See for yourself: build a logic gate from transistors in the simulator, then follow the path from sand to an 8-bit CPU.

Open the digiwleea lab →

Frequently asked

What is the difference between Verilog and SystemVerilog?

SystemVerilog (IEEE 1800) is the successor to Verilog (IEEE 1364) and includes it. It adds design features such as the logic type and always_ff and always_comb blocks, and verification features such as assertions, coverage, classes and constrained random testing.

Is SystemVerilog backward compatible with Verilog?

Largely: SystemVerilog was built as a superset of Verilog, so most Verilog code compiles as SystemVerilog. A few new keywords can clash with names used in old Verilog code.

Should I learn Verilog or SystemVerilog?

Learn the Verilog subset first, since it is the core of both, then add SystemVerilog's design features. Its verification features matter most if you will write testbenches for larger designs.

Is Verilog still used?

Yes, though its standard was folded into SystemVerilog in 2009. Many designs and tools still use the Verilog subset, and free tools such as Icarus Verilog target it.