cocotb, Chisel, Amaranth, SpinalHDL and MyHDL: hardware in Python and Scala

Beyond Verilog and VHDL, a family of open-source tools lets engineers design or test hardware from general-purpose languages. cocotb is a framework for writing VHDL and Verilog testbenches in Python: the design stays in an HDL, and the tests are Python. Chisel (Constructing Hardware in a Scala Embedded Language), from the CHIPS Alliance, adds hardware construction primitives to Scala and generates synthesizable Verilog. SpinalHDL is another Scala-based language that generates VHDL or Verilog, one to one with what you describe. Amaranth (previously nMigen) is a Python-based hardware definition language and toolchain with its own simulator and build system for FPGA work. MyHDL is a Python package for using Python as a hardware description and verification language. The first question is whether you want to verify existing HDL (cocotb) or generate the hardware itself (Chisel, SpinalHDL, Amaranth, MyHDL).

How to choose

If your design is already in Verilog or VHDL and you want richer tests, cocotb keeps the design as it is and lets you test it with Python's libraries. If you want parameterised generators for large designs and like Scala, Chisel (with its standard library of FIFOs and arbiters) or SpinalHDL. If you prefer Python and target FPGAs, Amaranth gives you the language, a simulator and the board build flow in one toolchain; MyHDL is the older Python option. All of them end in, or work alongside, standard HDL, so Verilog or VHDL knowledge still pays off. (digiwleea is an independent project, not affiliated with any of these projects.)

Where digiwleea fits

Every one of these tools describes registers, multiplexers, adders and state machines, which is what digiwleea teaches you to build by hand. In the browser you wire them from transistors up, through a 40+ level course with an AI tutor (Wleea), and every part is checked against its truth table or clocked behaviour; the free VHDL and Verilog lessons then write the same circuits as code. digiwleea does not run Python or Scala hardware descriptions; it is the place to understand what they generate.

Side by side

	Language	What it does	License
cocotb	Python	Testbenches for Verilog and VHDL designs	BSD-3-Clause
Chisel	Scala	Hardware generators that emit synthesizable Verilog	Apache-2.0
SpinalHDL	Scala	Hardware description that emits VHDL or Verilog	Free to use, including in industry (its README)
Amaranth	Python	HDL, standard library, simulator and FPGA build system	BSD-2-Clause
MyHDL	Python	Hardware description and verification in Python	LGPL

No sign-up is needed to start: open the lab and place your first transistor, or read the free theory course. The account (and the AI tutor) are optional.

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See for yourself: build a logic gate from transistors in the simulator, then follow the path from sand to an 8-bit CPU.

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Frequently asked

What is cocotb?

An open-source framework for writing testbenches for VHDL and Verilog designs in Python. The design stays in an HDL, simulated by a regular HDL simulator, while the test code is Python.

What is the difference between Chisel and Verilog?

Chisel is a hardware construction language embedded in Scala that generates synthesizable Verilog. You write generators in Scala, and the output is Verilog that standard tools can synthesize.

Is Amaranth the same as nMigen?

Yes. Amaranth HDL was previously called nMigen. It is a Python-based hardware definition language and toolchain.

Can I design hardware in Python?

Yes. Amaranth and MyHDL describe hardware in Python, and cocotb tests Verilog or VHDL designs from Python.